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/linux/drivers/clk/
H A Dclk-fixed-rate_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for clk fixed rate basic type
6 #include <linux/clk-provider.h>
17 #include "clk-fixed-rate_test.h"
20 * struct clk_hw_fixed_rate_kunit_params - Parameters to pass to __clk_hw_register_fixed_rate()
30 * @clk_fixed_flags: fixed rate specific clk flags
51 hw = __clk_hw_register_fixed_rate(params->dev, params->np, in clk_hw_register_fixed_rate_kunit_init()
52 params->name, in clk_hw_register_fixed_rate_kunit_init()
53 params->parent_name, in clk_hw_register_fixed_rate_kunit_init()
54 params->parent_hw, in clk_hw_register_fixed_rate_kunit_init()
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H A Dclk-fixed-rate.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
24 * parent - fixed parent. No clk_set_parent support
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H A Dclk-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/clk-provider.h>
26 * prepare - clk_(un)prepare are functional and control a gpio that can sleep
27 * enable - clk_enable and clk_disable are functional & control
28 * non-sleeping gpio
29 * rate - inherits rate from parent. No clk_set_rate support
30 * parent - fixed parent. No clk_set_parent support
34 * struct clk_gpio - gpio gated clock
36 * @hw: handle between common and hardware-specific interfaces
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H A Dclk-ep93xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Based on a rewrite of arch/arm/mach-ep93xx/clock.c:
13 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/cirrus,ep9301-syscon.h>
94 struct clk_hw *fixed[EP93XX_FIXED_CLK_COUNT]; member
105 return container_of(clk, struct ep93xx_clk_priv, reg[clk->idx]); in ep93xx_priv_from()
110 struct ep93xx_regmap_adev *aux = priv->aux_dev; in ep93xx_clk_write()
112 aux->write(aux->map, aux->lock, reg, val); in ep93xx_clk_write()
121 regmap_read(priv->map, clk->reg, &val); in ep93xx_clk_is_enabled()
123 return !!(val & BIT(clk->bit_idx)); in ep93xx_clk_is_enabled()
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H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
26 unsigned long long int rate; in clk_factor_recalc_rate() local
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
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H A Dclk-loongson1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Clock driver for Loongson-1 SoC
5 * Copyright (C) 2012-2023 Keguang Zhang <keguang.zhang@gmail.com>
9 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/loongson,ls1x-clk.h>
26 u32 fixed; member
64 const struct ls1x_clk_pll_data *d = ls1x_clk->data; in ls1x_pll_recalc_rate()
65 u32 val, rate; in ls1x_pll_recalc_rate() local
67 val = readl(ls1x_clk->reg); in ls1x_pll_recalc_rate()
68 rate = d->fixed; in ls1x_pll_recalc_rate()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
87 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
91 tristate "Raspberry Pi RP1-based clock support"
96 This multi-function device has 3 main PLLs and several clock
97 generators to drive the internal sub-peripherals.
106 multi-function device has one fixed-rate oscillator, clocked
137 be pre-programmed to support other configurations and features not yet
186 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
204 For example, the CDCE925 contains two PLLs with spread-spectrum
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/linux/drivers/clk/sunxi/
H A Dclk-a10-hosc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
20 struct clk_fixed_rate *fixed; in sun4i_osc_clk_setup() local
22 const char *clk_name = node->name; in sun4i_osc_clk_setup()
23 u32 rate; in sun4i_osc_clk_setup() local
25 if (of_property_read_u32(node, "clock-frequency", &rate)) in sun4i_osc_clk_setup()
28 /* allocate fixed-rate and gate clock structs */ in sun4i_osc_clk_setup()
29 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); in sun4i_osc_clk_setup()
30 if (!fixed) in sun4i_osc_clk_setup()
36 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_osc_clk_setup()
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H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
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/linux/drivers/clk/tegra/
H A Dclk-periph-fixed.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
19 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_is_enabled() local
20 u32 mask = 1 << (fixed->num % 32), value; in tegra_clk_periph_fixed_is_enabled()
22 value = readl(fixed->base + fixed->regs->enb_reg); in tegra_clk_periph_fixed_is_enabled()
24 value = readl(fixed->base + fixed->regs->rst_reg); in tegra_clk_periph_fixed_is_enabled()
34 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_enable() local
35 u32 mask = 1 << (fixed->num % 32); in tegra_clk_periph_fixed_enable()
37 writel(mask, fixed->base + fixed->regs->enb_set_reg); in tegra_clk_periph_fixed_enable()
44 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_disable() local
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dcanaan,k230-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ze Huang <18771902331@163.com>
15 performed on a per-pin basis.
19 const: canaan,k230-pinctrl
25 '-pins$':
33 '-cfg$':
36 - $ref: /schemas/pinctrl/pincfg-node.yaml
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/linux/drivers/clk/qcom/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/interconnect-clk.h>
13 #include <linux/reset-controller.h>
17 #include "clk-alpha-pll.h"
18 #include "clk-branch.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
32 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate) in qcom_find_freq() argument
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H A Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
8 * and supplies fixed rate clocks as output to the networking hardware
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
23 * +---------+
25 * +--+---+--+
28 * +-------+---+------+
29 * | +-------------> eth0-50mhz
31 * -------->+ +-------------> eth1-50mhz
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/linux/arch/mips/bcm63xx/
H A Dclk.c23 unsigned int rate; member
33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
355 .rate = (50 * 1000 * 1000),
403 return clk->rate; in clk_get_rate()
408 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
414 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
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/linux/drivers/clk/actions/
H A Dowl-pll.c1 // SPDX-License-Identifier: GPL-2.0+
6 // Author: David Liu <liuwei@actions-semi.com>
11 #include <linux/clk-provider.h>
16 #include "owl-pll.h"
18 static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate) in owl_pll_calculate_mul() argument
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); in owl_pll_calculate_mul()
23 if (mul < pll_hw->min_mul) in owl_pll_calculate_mul()
24 mul = pll_hw->min_mul; in owl_pll_calculate_mul()
25 else if (mul > pll_hw->max_mul) in owl_pll_calculate_mul()
26 mul = pll_hw->max_mul; in owl_pll_calculate_mul()
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/linux/Documentation/devicetree/bindings/clock/
H A Dfixed-mmio-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple memory mapped IO fixed-rate clock sources
10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I/O register.
17 - Jan Kotas <jank@cadence.com>
21 const: fixed-mmio-clock
26 "#clock-cells":
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H A Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
19 pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
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/linux/drivers/clk/davinci/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
78 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
85 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
89 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
95 * struct davinci_pll_clk - Main PLL clock (aka PLLOUT)
117 unsigned long rate = parent_rate; in davinci_pll_recalc_rate() local
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/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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/linux/sound/soc/
H A Dsoc-utils-test.c1 // SPDX-License-Identifier: GPL-2.0-only
13 u32 rate; member
21 /* rate fmt channels tdm_width tdm_slots slot_multiple bclk */
63 /* Fixed 8-slot TDM, other values from params */
81 /* Fixed 32-bit TDM, other values from params */
99 /* Fixed 6-slot 24-bit TDM, other values from params */
119 unsigned int rate, snd_pcm_format_t fmt, in test_tdm_params_to_bclk_one() argument
130 hw_param_interval(&params, SNDRV_PCM_HW_PARAM_RATE)->min = rate; in test_tdm_params_to_bclk_one()
131 hw_param_interval(&params, SNDRV_PCM_HW_PARAM_RATE)->max = rate; in test_tdm_params_to_bclk_one()
132 hw_param_interval(&params, SNDRV_PCM_HW_PARAM_CHANNELS)->min = channels; in test_tdm_params_to_bclk_one()
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/linux/drivers/clk/at91/
H A Dclk-audio-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Quentin Schulz <quentin.schulz@free-electrons.com>
10 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
11 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
12 * asked rate.
15 * enable - clk_enable writes nd, fracr parameters and enables PLL
16 * rate - rate is adjustable.
17 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
18 * parent - fixed parent. No clk_set_parent support
21 * enable - clk_enable writes qdpmc, and enables PMC output
[all …]
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-fixed-rate.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
10 #include "clk-uniphier.h"
16 struct clk_fixed_rate *fixed; in uniphier_clk_register_fixed_rate() local
20 /* allocate fixed-rate clock */ in uniphier_clk_register_fixed_rate()
21 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL); in uniphier_clk_register_fixed_rate()
22 if (!fixed) in uniphier_clk_register_fixed_rate()
23 return ERR_PTR(-ENOMEM); in uniphier_clk_register_fixed_rate()
31 fixed->fixed_rate = data->fixed_rate; in uniphier_clk_register_fixed_rate()
32 fixed->hw.init = &init; in uniphier_clk_register_fixed_rate()
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: regulator-pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]
/linux/drivers/clk/bcm/
H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
61 return (u64)div->u.fixed; in scaled_div_min()
72 return (u64)div->u.fixed; in scaled_div_max()
74 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
89 return (u32)(scaled_div - ((u64)1 << div->u.s.frac_width)); in divider()
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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
40 dma-names:
42 - const: rx
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