Lines Matching +full:fixed +full:- +full:rate
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
8 * and supplies fixed rate clocks as output to the networking hardware
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
23 * +---------+
25 * +--+---+--+
28 * +-------+---+------+
29 * | +-------------> eth0-50mhz
31 * -------->+ +-------------> eth1-50mhz
33 * | +-------------> eth2-50mhz
35 * +----+----+----+---+-------------> eth-25mhz
42 #include <linux/clk-provider.h>
52 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
53 #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
54 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
77 * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information
80 * @rate: Clock rate
85 unsigned long rate; member
89 * struct clk_cmn_pll - CMN PLL hardware specific data
91 * @hw: handle between common and hardware-specific interfaces
101 .rate = _rate, \
114 CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
115 CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
116 CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),
121 CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
122 CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
123 CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
124 CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
125 CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL),
126 CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
127 CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
128 CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
129 CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
134 CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
135 CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
136 CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
137 CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),
138 CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
139 CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
140 CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
141 CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
142 CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
148 * possible parent clock rates, each parent clock rate is reflected
153 int index = -EINVAL; in ipq_cmn_pll_find_freq_index()
168 * Parent clock rate 48 MHZ and 96 MHZ take the same value in ipq_cmn_pll_find_freq_index()
192 * by HW according to the parent clock rate. in clk_cmn_pll_recalc_rate()
194 regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val); in clk_cmn_pll_recalc_rate()
205 /* Validate the rate of the single parent clock. */ in clk_cmn_pll_determine_rate()
206 ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate); in clk_cmn_pll_determine_rate()
212 * This function is used to initialize the CMN PLL to enable the fixed
213 * rate output clocks. It is expected to be configured once.
215 static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate, in clk_cmn_pll_set_rate() argument
224 * parent clock. The output clock rates are always of fixed value. in clk_cmn_pll_set_rate()
230 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, in clk_cmn_pll_set_rate()
237 * Update the source clock rate selection and source clock in clk_cmn_pll_set_rate()
238 * divider as 2 when the parent clock rate is 96 MHZ. in clk_cmn_pll_set_rate()
241 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, in clk_cmn_pll_set_rate()
247 ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION, in clk_cmn_pll_set_rate()
255 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_CTRL, in clk_cmn_pll_set_rate()
264 ret = regmap_clear_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, in clk_cmn_pll_set_rate()
270 ret = regmap_set_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET, in clk_cmn_pll_set_rate()
276 return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val, in clk_cmn_pll_set_rate()
290 struct device *dev = &pdev->dev; in ipq_cmn_pll_clk_hw_register()
307 return ERR_PTR(-ENOMEM); in ipq_cmn_pll_clk_hw_register()
314 cmn_pll->hw.init = &init; in ipq_cmn_pll_clk_hw_register()
315 cmn_pll->regmap = regmap; in ipq_cmn_pll_clk_hw_register()
317 ret = devm_clk_hw_register(dev, &cmn_pll->hw); in ipq_cmn_pll_clk_hw_register()
321 return &cmn_pll->hw; in ipq_cmn_pll_clk_hw_register()
328 struct device *dev = &pdev->dev; in ipq_cmn_pll_register_clks()
336 return -EINVAL; in ipq_cmn_pll_register_clks()
339 for (p = fixed_clk; p->name; p++) in ipq_cmn_pll_register_clks()
345 return -ENOMEM; in ipq_cmn_pll_register_clks()
349 * the fixed rate output clocks. in ipq_cmn_pll_register_clks()
355 /* Register the fixed rate output clocks. */ in ipq_cmn_pll_register_clks()
359 fixed_clk[i].rate); in ipq_cmn_pll_register_clks()
365 hw_data->hws[fixed_clk[i].id] = hw; in ipq_cmn_pll_register_clks()
369 * Provide the CMN PLL clock. The clock rate of CMN PLL in ipq_cmn_pll_register_clks()
370 * is configured to 12 GHZ by DT property assigned-clock-rates-u64. in ipq_cmn_pll_register_clks()
372 hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw; in ipq_cmn_pll_register_clks()
373 hw_data->num = num_clks + 1; in ipq_cmn_pll_register_clks()
385 clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); in ipq_cmn_pll_register_clks()
392 struct device *dev = &pdev->dev; in ipq_cmn_pll_clk_probe()
419 /* Register CMN PLL clock and fixed rate output clocks. */ in ipq_cmn_pll_clk_probe()
438 for (i = 0; i < hw_data->num; i++) { in ipq_cmn_pll_clk_remove()
440 clk_hw_unregister(hw_data->hws[i]); in ipq_cmn_pll_clk_remove()
449 { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },
450 { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
451 { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },