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/linux/arch/arm/boot/dts/ti/omap/
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
27 #clock-cells = <2>;
28 #address-cells = <1>;
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
26 ti,max-div = <3>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
26 #clock-cells = <0>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
[all …]
H A Ddm814x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
[all …]
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
31 #clock-cells = <0>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
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/linux/Documentation/devicetree/bindings/clock/
H A Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
19 pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
24 #clock-cells = <0>;
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/linux/drivers/media/platform/st/sti/bdisp/
H A Dbdisp-filter.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * struct bdisp_filter_h_spec - Horizontal filter specification
13 * @min: min scale factor for this filter (6.10 fixed point)
14 * @max: max scale factor for this filter (6.10 fixed point)
23 * struct bdisp_filter_v_spec - Vertical filter specification
25 * @min: min scale factor for this filter (6.10 fixed point)
26 * @max: max scale factor for this filter (6.10 fixed point)
/linux/Documentation/devicetree/bindings/mfd/
H A Dallwinner,sun8i-a23-prcm.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 const: allwinner,sun8i-a23-prcm
30 - fixed-factor-clock
31 - allwinner,sun8i-a23-apb0-clk
32 - allwinner,sun8i-a23-apb0-gates-clk
[all …]
/linux/drivers/clk/ti/
H A Dfixed-factor.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Fixed Factor Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
23 * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
26 * Sets up a simple fixed factor clock based on device tree info.
36 if (of_property_read_u32(node, "ti,clock-div", &div)) { in of_ti_fixed_factor_clk_setup()
37 pr_err("%pOFn must have a clock-div property\n", node); in of_ti_fixed_factor_clk_setup()
41 if (of_property_read_u32(node, "ti,clock-mult", &mult)) { in of_ti_fixed_factor_clk_setup()
42 pr_err("%pOFn must have a clock-mult property\n", node); in of_ti_fixed_factor_clk_setup()
[all …]
/linux/drivers/clk/
H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
43 return -EINVAL; in clk_factor_determine_rate()
[all …]
/linux/drivers/clk/qcom/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/interconnect-clk.h>
13 #include <linux/reset-controller.h>
17 #include "clk-alpha-pll.h"
18 #include "clk-branch.h"
19 #include "clk-rcg.h"
20 #include "clk-regmap.h"
37 if (!f->freq) in qcom_find_freq()
[all …]
H A Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
8 * and supplies fixed rate clocks as output to the networking hardware
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
25 * MHZ clock to the PPE. The remaining fixed-rate clocks to the GCC and PCS
28 * +---------+
30 * +--+---+--+
33 * +-------+---+------+
34 * | +-------------> eth0-50mhz
36 * -------->+ +-------------> eth1-50mhz
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-cygnus-clock.dtsi34 #address-cells = <1>;
35 #size-cells = <1>;
39 #clock-cells = <0>;
40 compatible = "fixed-clock";
41 clock-frequency = <25000000>;
46 #clock-cells = <0>;
47 compatible = "brcm,cygnus-armpll";
54 #clock-cells = <0>;
55 compatible = "fixed-factor-clock";
57 clock-div = <2>;
[all …]
H A Dbcm5301x.dtsi9 #include "bcm-ns.dtsi"
12 mpcore-bus@19000000 {
14 #clock-cells = <0>;
15 compatible = "brcm,nsp-armpll";
21 compatible = "arm,cortex-a9-twd-wdt";
30 #address-cells = <1>;
31 #size-cells = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
[all …]
/linux/drivers/clk/samsung/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include <linux/device-id/of.h>
16 #include "clk-pll.h"
17 #include "clk-cpu.h"
20 * struct samsung_clk_provider - information about clock provider
23 * @sysreg: syscon regmap for clock-provider sysreg controller
24 * @lock: maintains exclusion between callbacks for a given clock-provider
25 * @auto_clock_gate: enable auto clk mode for all clocks in clock-provider
27 * @option_offset: option reg offset. Enables auto mode for clock-provider
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dmps2.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include "../armv7-m.dtsi"
48 #address-cells = <1>;
49 #size-cells = <1>;
51 oscclk0: clock-50000000 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <50000000>;
57 oscclk1: clock-24576000 {
58 compatible = "fixed-clock";
[all …]
H A Dintegratorcp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
11 compatible = "arm,integrator-cp";
18 #address-cells = <1>;
19 #size-cells = <0>;
35 operating-points = <50000 0
38 clock-names = "cpu";
39 clock-latency = <1000000>; /* 1 ms */
45 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
50 xtal_codec: clock-24576000 {
[all …]
/linux/drivers/staging/media/atomisp/pci/isp/kernels/xnr/xnr_3.0/
H A Dia_css_xnr3.host.c1 // SPDX-License-Identifier: GPL-2.0
17 #define XNR_MAX_ALPHA ((1 << (ISP_VEC_ELEMBITS - 1)) - 1)
25 * division look-up table
36 -7213, -5580, -4371, -3421, -2722, -2159, -6950, -5585,
37 -4529, -3697, -3010, -2485, -2070, -1727, -1428, 0
96 s32 offset = host_scale / 2; /* fixed-point 0.5 */ in compute_coring()
98 /* Convert from public host-side scale factor to isp-side scale in compute_coring()
99 * factor. Clip to [0, isp_scale-1). in compute_coring()
102 return clamp(isp_coring, 0, isp_scale - 1); in compute_coring()
115 s32 offset = host_scale / 2; /* fixed-point 0.5 */ in compute_blending()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h1 /* SPDX-License-Identifier: MIT */
41 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
56 /* Read-only state that reports all features enabled */
58 /* Read-only state that reports that Macrovision is disabled in hardware*/
60 /* Read-only state that reports that TV-out is disabled in hardware. */
64 /* Encoder test pattern 1 - combo pattern */
66 /* Encoder test pattern 2 - full screen vertical 75% color bars */
68 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
70 /* Encoder test pattern 4 - random noise */
72 /* Encoder test pattern 5 - linear color ramps */
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
[all …]

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