xref: /linux/arch/arm/boot/dts/broadcom/bcm5301x.dtsi (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1*724ba675SRob Herring/*
2*724ba675SRob Herring * Broadcom BCM470X / BCM5301X ARM platform code.
3*724ba675SRob Herring * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4*724ba675SRob Herring * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
5*724ba675SRob Herring *
6*724ba675SRob Herring * Licensed under the GNU/GPL. See COPYING for details.
7*724ba675SRob Herring */
8*724ba675SRob Herring
9*724ba675SRob Herring#include "bcm-ns.dtsi"
10*724ba675SRob Herring
11*724ba675SRob Herring/ {
12*724ba675SRob Herring	mpcore-bus@19000000 {
13*724ba675SRob Herring		a9pll: arm_clk@0 {
14*724ba675SRob Herring			#clock-cells = <0>;
15*724ba675SRob Herring			compatible = "brcm,nsp-armpll";
16*724ba675SRob Herring			clocks = <&osc>;
17*724ba675SRob Herring			reg = <0x00000 0x1000>;
18*724ba675SRob Herring		};
19*724ba675SRob Herring
20*724ba675SRob Herring		watchdog@20620 {
21*724ba675SRob Herring			compatible = "arm,cortex-a9-twd-wdt";
22*724ba675SRob Herring			reg = <0x20620 0x20>;
23*724ba675SRob Herring			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
24*724ba675SRob Herring						  IRQ_TYPE_EDGE_RISING)>;
25*724ba675SRob Herring			clocks = <&periph_clk>;
26*724ba675SRob Herring		};
27*724ba675SRob Herring	};
28*724ba675SRob Herring
29*724ba675SRob Herring	clocks {
30*724ba675SRob Herring		#address-cells = <1>;
31*724ba675SRob Herring		#size-cells = <1>;
32*724ba675SRob Herring		ranges;
33*724ba675SRob Herring
34*724ba675SRob Herring		osc: oscillator {
35*724ba675SRob Herring			#clock-cells = <0>;
36*724ba675SRob Herring			compatible = "fixed-clock";
37*724ba675SRob Herring			clock-frequency = <25000000>;
38*724ba675SRob Herring		};
39*724ba675SRob Herring
40*724ba675SRob Herring		iprocmed: iprocmed {
41*724ba675SRob Herring			#clock-cells = <0>;
42*724ba675SRob Herring			compatible = "fixed-factor-clock";
43*724ba675SRob Herring			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
44*724ba675SRob Herring			clock-div = <2>;
45*724ba675SRob Herring			clock-mult = <1>;
46*724ba675SRob Herring		};
47*724ba675SRob Herring
48*724ba675SRob Herring		iprocslow: iprocslow {
49*724ba675SRob Herring			#clock-cells = <0>;
50*724ba675SRob Herring			compatible = "fixed-factor-clock";
51*724ba675SRob Herring			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
52*724ba675SRob Herring			clock-div = <4>;
53*724ba675SRob Herring			clock-mult = <1>;
54*724ba675SRob Herring		};
55*724ba675SRob Herring
56*724ba675SRob Herring		periph_clk: periph_clk {
57*724ba675SRob Herring			#clock-cells = <0>;
58*724ba675SRob Herring			compatible = "fixed-factor-clock";
59*724ba675SRob Herring			clocks = <&a9pll>;
60*724ba675SRob Herring			clock-div = <2>;
61*724ba675SRob Herring			clock-mult = <1>;
62*724ba675SRob Herring		};
63*724ba675SRob Herring	};
64*724ba675SRob Herring
65*724ba675SRob Herring	i2c0: i2c@18009000 {
66*724ba675SRob Herring		compatible = "brcm,iproc-i2c";
67*724ba675SRob Herring		reg = <0x18009000 0x50>;
68*724ba675SRob Herring		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
69*724ba675SRob Herring		#address-cells = <1>;
70*724ba675SRob Herring		#size-cells = <0>;
71*724ba675SRob Herring		clock-frequency = <100000>;
72*724ba675SRob Herring		status = "disabled";
73*724ba675SRob Herring	};
74*724ba675SRob Herring
75*724ba675SRob Herring	dmu-bus@1800c000 {
76*724ba675SRob Herring		cru-bus@100 {
77*724ba675SRob Herring			lcpll0: clock-controller@100 {
78*724ba675SRob Herring				#clock-cells = <1>;
79*724ba675SRob Herring				compatible = "brcm,nsp-lcpll0";
80*724ba675SRob Herring				reg = <0x100 0x14>;
81*724ba675SRob Herring				clocks = <&osc>;
82*724ba675SRob Herring				clock-output-names = "lcpll0", "pcie_phy",
83*724ba675SRob Herring						     "sdio", "ddr_phy";
84*724ba675SRob Herring			};
85*724ba675SRob Herring
86*724ba675SRob Herring			genpll: clock-controller@140 {
87*724ba675SRob Herring				#clock-cells = <1>;
88*724ba675SRob Herring				compatible = "brcm,nsp-genpll";
89*724ba675SRob Herring				reg = <0x140 0x24>;
90*724ba675SRob Herring				clocks = <&osc>;
91*724ba675SRob Herring				clock-output-names = "genpll", "phy",
92*724ba675SRob Herring						     "ethernetclk",
93*724ba675SRob Herring						     "usbclk", "iprocfast",
94*724ba675SRob Herring						     "sata1", "sata2";
95*724ba675SRob Herring			};
96*724ba675SRob Herring		};
97*724ba675SRob Herring	};
98*724ba675SRob Herring
99*724ba675SRob Herring	spi@18029200 {
100*724ba675SRob Herring		compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
101*724ba675SRob Herring		reg = <0x18029200 0x184>,
102*724ba675SRob Herring		      <0x18029000 0x124>,
103*724ba675SRob Herring		      <0x1811b408 0x004>,
104*724ba675SRob Herring		      <0x180293a0 0x01c>;
105*724ba675SRob Herring		reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
106*724ba675SRob Herring		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
107*724ba675SRob Herring			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
108*724ba675SRob Herring			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
109*724ba675SRob Herring			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
110*724ba675SRob Herring			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
111*724ba675SRob Herring			     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
112*724ba675SRob Herring			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
113*724ba675SRob Herring		interrupt-names = "mspi_done",
114*724ba675SRob Herring				  "mspi_halted",
115*724ba675SRob Herring				  "spi_lr_fullness_reached",
116*724ba675SRob Herring				  "spi_lr_session_aborted",
117*724ba675SRob Herring				  "spi_lr_impatient",
118*724ba675SRob Herring				  "spi_lr_session_done",
119*724ba675SRob Herring				  "spi_lr_overread";
120*724ba675SRob Herring		clocks = <&iprocmed>;
121*724ba675SRob Herring		num-cs = <2>;
122*724ba675SRob Herring		#address-cells = <1>;
123*724ba675SRob Herring		#size-cells = <0>;
124*724ba675SRob Herring
125*724ba675SRob Herring		spi_nor: flash@0 {
126*724ba675SRob Herring			compatible = "jedec,spi-nor";
127*724ba675SRob Herring			reg = <0>;
128*724ba675SRob Herring			spi-max-frequency = <20000000>;
129*724ba675SRob Herring			status = "disabled";
130*724ba675SRob Herring
131*724ba675SRob Herring			partitions {
132*724ba675SRob Herring				compatible = "brcm,bcm947xx-cfe-partitions";
133*724ba675SRob Herring			};
134*724ba675SRob Herring		};
135*724ba675SRob Herring	};
136*724ba675SRob Herring};
137