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/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
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/linux/include/linux/soc/qcom/
H A Dgeni-se.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
16 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
58 * struct geni_se - GENI Serial Engine
270 * For QUP HW Version >= 3.10 Tx fifo depth support is increased
271 * to 256bytes and corresponding bits ar
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
21 - sifive,fu540-c000-spi
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/linux/drivers/net/ethernet/sgi/
H A Dmeth.h4 #define TX_RING_ENTRIES 64 /* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
32 * It consists of header, 0-3 concatination
43 u64 data_len:16; /*Length of valid data in bytes-1*/
48 u64 len:16; /*length of buffer data - 1*/
91 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
99 /* Bits in METH_MAC */
110 /* Bits 5 and 6 are used to determine the Destination address filter mode */
122 … /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
[all …]
/linux/drivers/spi/
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
25 #define CDNS_SPI_NAME "cdns-spi"
38 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
44 * This register contains various control bits that affect the operation
63 * SPI Configuration Register - Baud rate and target select
82 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
84 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
102 * struct cdns_spi - This definition defines spi driver instance
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H A Dspi-hisi-kunpeng.c1 // SPDX-License-Identifier: GPL-2.0-only
8 // This code is based on spi-dw-core.c.
26 #define HISI_SPI_FIFOC 0x0c /* fifo level control register */
49 /* Bit fields in HISI_SPI_IMR, 4 bits */
56 /* Bit fields in HISI_SPI_SR, 5 bits */
57 #define SR_TXE BIT(0) /* Transmit FIFO empty */
58 #define SR_TXNF BIT(1) /* Transmit FIFO not full */
59 #define SR_RXNE BIT(2) /* Receive FIFO not empty */
60 #define SR_RXF BIT(3) /* Receive FIFO full */
63 /* Bit fields in HISI_SPI_ISR, 4 bits */
[all …]
H A Dspi-dw.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/bits.h>
11 #include <linux/spi/spi-mem.h>
14 /* Synopsys DW SSI IP-core virtual IDs */
21 /* DW SSI IP-core ID and version check helpers */
23 ((_dws)->ip == DW_ ## _ip ## _ID)
26 (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
36 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
101 /* Bit fields in SR, 7 bits */
111 /* Bit fields in ISR, IMR, RISR, 7 bits */
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
[all …]
/linux/include/media/drv-intf/
H A Dexynos-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
12 #include <media/media-entity.h>
13 #include <media/v4l2-dev.h>
14 #include <media/v4l2-mediabus.h>
37 /* Camera MIPI-CSI2 serial bus */
39 /* FIFO link from LCD controller (WriteBack A) */
41 /* FIFO link from LCD controller (WriteBack B) */
43 /* FIFO link from FIMC-IS */
62 * struct fimc_source_info - video source description required for the host
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/linux/arch/nios2/boot/dts/
H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
H A D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
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/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
38 /* ----------------------------
40 * ----------------------------
49 /* ----------------------------
51 * ----------------------------
70 /* ----------------------------
72 * ----------------------------
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/linux/sound/soc/fsl/
H A Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
16 #include <linux/dma-mapping.h>
40 * that is 8, 16, or 32 bits.
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
120 * Since each link descriptor has a 32-bit byte count field, we set
121 * period_bytes_max to the largest 32-bit number. We also have no maximum
137 .period_bytes_max = (u32) -1,
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H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
13 // one FIFO which combines all valid receive slots. We cannot even select
16 // we receive in our (PCM-) data stream. The only chance we have is to
23 // provides us status bits when the read register is updated with *another*
25 // contains the same value) these status bits are not set. We work
26 // around this by not polling these bits but only wait a fixed delay.
43 #include <linux/dma/imx-dma.h>
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/linux/arch/arm/boot/dts/rockchip/
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
H A Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
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/linux/drivers/tty/serial/
H A Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
17 * - The tree/master/src/main/scala/devices/uart directory of
[all …]
/linux/drivers/video/fbdev/aty/
H A Dmach64_accel.c1 // SPDX-License-Identifier: GPL-2.0
49 /* ensure engine is not locked up by clearing any FIFO or */ in aty_reset_engine()
54 par->fifo_space = 0; in aty_reset_engine()
73 pitch_value = info->fix.line_length / (info->var.bits_per_pixel / 8); in aty_init_engine()
74 vxres = info->var.xres_virtual; in aty_init_engine()
76 if (info->var.bits_per_pixel == 24) { in aty_init_engine()
77 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ in aty_init_engine()
89 /* Ensure that vga page pointers are set to zero - the upper */ in aty_init_engine()
95 /* ---- Setup standard engine context ---- */ in aty_init_engine()
97 /* All GUI registers here are FIFOed - therefore, wait for */ in aty_init_engine()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include <linux/bits.h>
192 * struct dw_i2c_dev - private i2c-designware data
220 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support
223 * @tx_fifo_depth: depth of the hardware tx fifo
224 * @rx_fifo_depth: depth of the hardware rx fifo
225 * @rx_outstanding: current master-rx elements in tx fifo
239 * -1 if there is no semaphore.
243 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
355 dev->status |= STATUS_ACTIVE; in __i2c_dw_enable()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw700x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/net/ti-dp83867.h>
22 gpio-keys {
23 compatible = "gpio-keys";
25 key-user-pb {
31 key-user-pb1x {
34 interrupt-parent = <&gsc>;
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 u-boot {
13 compatible = "u-boot,config";
14 bootscr-address = /bits/ 64 <0x3000000>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/linux/drivers/comedi/drivers/
H A Dmite.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
11 * The PCI-MIO E series driver was originally written by
18 * DAQ-STC reference manual
27 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
28 * 321808a.pdf about at-mio-16e-10 rev P
29 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
30 * 321838a.pdf about at-mio-16de-10 rev N
73 #define CHOR_ABORT BIT(3) /* stop without emptying fifo */
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
171 * @dfifodepth: DFIFO Depth (DfifoDepth)
172 * This value is in terms of 32-bit words.
[all …]
/linux/drivers/media/i2c/
H A Dtda1997x_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
165 #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */
166 #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */
212 #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */
227 /* Page 0x01 - HDMI info and packets */
244 #define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */
245 #define HDMI_FLAGS_AUD_FIFO_LOW BIT(0) /* FIFO read ptr within 2 of write */
247 /* Page 0x12 - HDMI Extra control and debug */
279 /* Page 0x13 - HDMI Extra control and debug */
[all …]

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