Lines Matching +full:fifo +full:- +full:depth +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0
6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 compatible = "xlnx,versal-net";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
21 u-boot {
22 compatible = "u-boot,config";
23 bootscr-address = /bits/ 64 <0x20000000>;
28 #address-cells = <1>;
29 #size-cells = <0>;
30 cpu-map {
101 compatible = "arm,cortex-a78";
103 enable-method = "psci";
105 operating-points-v2 = <&cpu_opp_table>;
106 cpu-idle-states = <&CPU_SLEEP_0>;
109 compatible = "arm,cortex-a78";
111 enable-method = "psci";
113 operating-points-v2 = <&cpu_opp_table>;
114 cpu-idle-states = <&CPU_SLEEP_0>;
117 compatible = "arm,cortex-a78";
119 enable-method = "psci";
121 operating-points-v2 = <&cpu_opp_table>;
122 cpu-idle-states = <&CPU_SLEEP_0>;
125 compatible = "arm,cortex-a78";
127 enable-method = "psci";
129 operating-points-v2 = <&cpu_opp_table>;
130 cpu-idle-states = <&CPU_SLEEP_0>;
133 compatible = "arm,cortex-a78";
135 enable-method = "psci";
137 operating-points-v2 = <&cpu_opp_table>;
138 cpu-idle-states = <&CPU_SLEEP_0>;
141 compatible = "arm,cortex-a78";
143 enable-method = "psci";
145 operating-points-v2 = <&cpu_opp_table>;
146 cpu-idle-states = <&CPU_SLEEP_0>;
149 compatible = "arm,cortex-a78";
151 enable-method = "psci";
153 operating-points-v2 = <&cpu_opp_table>;
154 cpu-idle-states = <&CPU_SLEEP_0>;
157 compatible = "arm,cortex-a78";
159 enable-method = "psci";
161 operating-points-v2 = <&cpu_opp_table>;
162 cpu-idle-states = <&CPU_SLEEP_0>;
165 compatible = "arm,cortex-a78";
167 enable-method = "psci";
169 operating-points-v2 = <&cpu_opp_table>;
170 cpu-idle-states = <&CPU_SLEEP_0>;
173 compatible = "arm,cortex-a78";
175 enable-method = "psci";
177 operating-points-v2 = <&cpu_opp_table>;
178 cpu-idle-states = <&CPU_SLEEP_0>;
181 compatible = "arm,cortex-a78";
183 enable-method = "psci";
185 operating-points-v2 = <&cpu_opp_table>;
186 cpu-idle-states = <&CPU_SLEEP_0>;
189 compatible = "arm,cortex-a78";
191 enable-method = "psci";
193 operating-points-v2 = <&cpu_opp_table>;
194 cpu-idle-states = <&CPU_SLEEP_0>;
197 compatible = "arm,cortex-a78";
199 enable-method = "psci";
201 operating-points-v2 = <&cpu_opp_table>;
202 cpu-idle-states = <&CPU_SLEEP_0>;
205 compatible = "arm,cortex-a78";
207 enable-method = "psci";
209 operating-points-v2 = <&cpu_opp_table>;
210 cpu-idle-states = <&CPU_SLEEP_0>;
213 compatible = "arm,cortex-a78";
215 enable-method = "psci";
217 operating-points-v2 = <&cpu_opp_table>;
218 cpu-idle-states = <&CPU_SLEEP_0>;
221 compatible = "arm,cortex-a78";
223 enable-method = "psci";
225 operating-points-v2 = <&cpu_opp_table>;
226 cpu-idle-states = <&CPU_SLEEP_0>;
228 idle-states {
229 entry-method = "psci";
231 CPU_SLEEP_0: cpu-sleep-0 {
232 compatible = "arm,idle-state";
233 arm,psci-suspend-param = <0x40000000>;
234 local-timer-stop;
235 entry-latency-us = <300>;
236 exit-latency-us = <600>;
237 min-residency-us = <10000>;
242 cpu_opp_table: opp-table {
243 compatible = "operating-points-v2";
244 opp-1066000000 {
245 opp-hz = /bits/ 64 <1066000000>;
246 opp-microvolt = <1000000>;
247 clock-latency-ns = <500000>;
249 opp-1866000000 {
250 opp-hz = /bits/ 64 <1866000000>;
251 opp-microvolt = <1000000>;
252 clock-latency-ns = <500000>;
254 opp-1900000000 {
255 opp-hz = /bits/ 64 <1900000000>;
256 opp-microvolt = <1000000>;
257 clock-latency-ns = <500000>;
259 opp-1999000000 {
260 opp-hz = /bits/ 64 <1999000000>;
261 opp-microvolt = <1000000>;
262 clock-latency-ns = <500000>;
264 opp-2050000000 {
265 opp-hz = /bits/ 64 <2050000000>;
266 opp-microvolt = <1000000>;
267 clock-latency-ns = <500000>;
269 opp-2100000000 {
270 opp-hz = /bits/ 64 <2100000000>;
271 opp-microvolt = <1000000>;
272 clock-latency-ns = <500000>;
274 opp-2200000000 {
275 opp-hz = /bits/ 64 <2200000000>;
276 opp-microvolt = <1000000>;
277 clock-latency-ns = <500000>;
279 opp-2400000000 {
280 opp-hz = /bits/ 64 <2400000000>;
281 opp-microvolt = <1000000>;
282 clock-latency-ns = <500000>;
304 bootph-all;
309 compatible = "arm,psci-1.0";
314 fpga: fpga-region {
315 compatible = "fpga-region";
316 fpga-mgr = <&versal_fpga>;
317 #address-cells = <2>;
318 #size-cells = <2>;
322 compatible = "arm,armv8-timer";
326 versal_fpga: versal-fpga {
327 compatible = "xlnx,versal-fpga";
331 compatible = "simple-bus";
332 bootph-all;
333 #address-cells = <2>;
334 #size-cells = <2>;
337 adma0: dma-controller@ebd00000 {
338 compatible = "xlnx,zynqmp-dma-1.0";
342 clock-names = "clk_main", "clk_apb";
343 #dma-cells = <1>;
344 xlnx,bus-width = <64>;
347 adma1: dma-controller@ebd10000 {
348 compatible = "xlnx,zynqmp-dma-1.0";
352 clock-names = "clk_main", "clk_apb";
353 #dma-cells = <1>;
354 xlnx,bus-width = <64>;
357 adma2: dma-controller@ebd20000 {
358 compatible = "xlnx,zynqmp-dma-1.0";
362 clock-names = "clk_main", "clk_apb";
363 #dma-cells = <1>;
364 xlnx,bus-width = <64>;
367 adma3: dma-controller@ebd30000 {
368 compatible = "xlnx,zynqmp-dma-1.0";
372 clock-names = "clk_main", "clk_apb";
373 #dma-cells = <1>;
374 xlnx,bus-width = <64>;
377 adma4: dma-controller@ebd40000 {
378 compatible = "xlnx,zynqmp-dma-1.0";
382 clock-names = "clk_main", "clk_apb";
383 #dma-cells = <1>;
384 xlnx,bus-width = <64>;
387 adma5: dma-controller@ebd50000 {
388 compatible = "xlnx,zynqmp-dma-1.0";
392 clock-names = "clk_main", "clk_apb";
393 #dma-cells = <1>;
394 xlnx,bus-width = <64>;
397 adma6: dma-controller@ebd60000 {
398 compatible = "xlnx,zynqmp-dma-1.0";
402 clock-names = "clk_main", "clk_apb";
403 #dma-cells = <1>;
404 xlnx,bus-width = <64>;
407 adma7: dma-controller@ebd70000 {
408 compatible = "xlnx,zynqmp-dma-1.0";
412 clock-names = "clk_main", "clk_apb";
413 #dma-cells = <1>;
414 xlnx,bus-width = <64>;
418 compatible = "xlnx,canfd-2.0";
422 clock-names = "can_clk", "s_axi_aclk";
423 rx-fifo-depth = <64>;
424 tx-mailbox-count = <32>;
428 compatible = "xlnx,canfd-2.0";
432 clock-names = "can_clk", "s_axi_aclk";
433 rx-fifo-depth = <64>;
434 tx-mailbox-count = <32>;
438 compatible = "xlnx,versal-gem", "cdns,gem";
442 clock-names = "pclk", "hclk", "tx_clk", "rx_clk",
447 compatible = "xlnx,versal-gem", "cdns,gem";
451 clock-names = "pclk", "hclk", "tx_clk", "rx_clk",
455 gic: interrupt-controller@e2000000 {
456 compatible = "arm,gic-v3";
457 #interrupt-cells = <3>;
460 interrupt-controller;
462 #address-cells = <2>;
463 #size-cells = <2>;
465 its: msi-controller@e2040000 {
466 compatible = "arm,gic-v3-its";
467 msi-controller;
468 #msi-cells = <1>;
474 compatible = "xlnx,versal-gpio-1.0";
478 #gpio-cells = <2>;
479 gpio-controller;
480 #interrupt-cells = <2>;
481 interrupt-controller;
485 compatible = "xlnx,pmc-gpio-1.0";
489 #gpio-cells = <2>;
490 gpio-controller;
491 #interrupt-cells = <2>;
492 interrupt-controller;
496 compatible = "cdns,i2c-r1p14";
500 clock-frequency = <400000>;
501 #address-cells = <1>;
502 #size-cells = <0>;
506 compatible = "cdns,i2c-r1p14";
510 clock-frequency = <400000>;
511 #address-cells = <1>;
512 #size-cells = <0>;
516 compatible = "snps,dw-i3c-master-1.00a";
519 #address-cells = <3>;
520 #size-cells = <0>;
525 compatible = "snps,dw-i3c-master-1.00a";
528 #address-cells = <3>;
529 #size-cells = <0>;
534 compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor";
539 cdns,fifo-depth = <256>;
540 cdns,fifo-width = <4>;
541 cdns,is-dma = <1>; /* u-boot specific */
542 cdns,trigger-address = <0xc0000000>;
546 compatible = "xlnx,versal-qspi-1.0";
550 clock-names = "ref_clk", "pclk";
554 compatible = "xlnx,zynqmp-rtc";
558 interrupt-names = "alarm", "sec";
563 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
567 clock-names = "clk_xin", "clk_ahb", "gate";
568 #clock-cells = <1>;
569 clock-output-names = "clk_out_sd0", "clk_in_sd0";
573 compatible = "xlnx,versal-net-emmc";
577 clock-names = "clk_xin", "clk_ahb", "gate";
578 #clock-cells = <1>;
579 clock-output-names = "clk_out_sd1", "clk_in_sd1";
583 bootph-all;
588 reg-io-width = <4>;
589 clock-names = "uartclk", "apb_pclk";
593 bootph-all;
598 reg-io-width = <4>;
599 clock-names = "uartclk", "apb_pclk";
603 compatible = "arm,smmu-v3";
606 #iommu-cells = <1>;
607 interrupt-names = "combined";
609 dma-coherent;
613 compatible = "cdns,spi-r1p6";
617 clock-names = "ref_clk", "pclk";
621 compatible = "cdns,spi-r1p6";
625 clock-names = "ref_clk", "pclk";
632 timer-width = <32>;
640 timer-width = <32>;
648 timer-width = <32>;
656 timer-width = <32>;
661 compatible = "xlnx,versal-dwc3";
664 clock-names = "bus_clk", "ref_clk";
666 #address-cells = <2>;
667 #size-cells = <2>;
673 interrupt-names = "host", "peripheral", "otg", "wakeup";
677 snps,quirk-frame-length-adjustment = <0x20>;
679 maximum-speed = "high-speed";
681 clock-names = "ref";
686 compatible = "xlnx,versal-dwc3";
689 clock-names = "bus_clk", "ref_clk";
691 #address-cells = <2>;
692 #size-cells = <2>;
698 interrupt-names = "host", "peripheral", "otg", "wakeup";
702 snps,quirk-frame-length-adjustment = <0x20>;
704 maximum-speed = "high-speed";
706 clock-names = "ref";
711 compatible = "xlnx,versal-wwdt";
714 timeout-sec = <30>;
718 compatible = "xlnx,versal-wwdt";
721 timeout-sec = <30>;
725 compatible = "xlnx,versal-wwdt";
728 timeout-sec = <30>;
732 compatible = "xlnx,versal-wwdt";
735 timeout-sec = <30>;
739 compatible = "xlnx,versal-wwdt";
742 timeout-sec = <30>;
746 compatible = "xlnx,versal-wwdt";
749 timeout-sec = <30>;