Lines Matching +full:fifo +full:- +full:depth +full:- +full:bits
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a7";
36 #cooling-cells = <2>; /* min followed by max */
37 dynamic-power-coefficient = <75>;
38 operating-points-v2 = <&cpu_opp_table>;
42 cpu_opp_table: opp-table-0 {
43 compatible = "operating-points-v2";
45 opp-408000000 {
46 opp-hz = /bits/ 64 <408000000>;
47 opp-microvolt = <975000>;
48 clock-latency-ns = <40000>;
50 opp-600000000 {
51 opp-hz = /bits/ 64 <600000000>;
52 opp-microvolt = <975000>;
53 clock-latency-ns = <40000>;
55 opp-816000000 {
56 opp-hz = /bits/ 64 <816000000>;
57 opp-microvolt = <1025000>;
58 clock-latency-ns = <40000>;
60 opp-1008000000 {
61 opp-hz = /bits/ 64 <1008000000>;
62 opp-microvolt = <1150000>;
63 clock-latency-ns = <40000>;
67 arm-pmu {
68 compatible = "arm,cortex-a7-pmu";
73 compatible = "arm,armv7-timer";
76 arm,cpu-registers-not-fw-configured;
77 clock-frequency = <24000000>;
81 compatible = "fixed-clock";
82 clock-frequency = <24000000>;
83 clock-output-names = "xin24m";
84 #clock-cells = <0>;
88 compatible = "mmio-sram";
90 #address-cells = <1>;
91 #size-cells = <1>;
96 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
99 reg-shift = <2>;
100 reg-io-width = <4>;
101 clock-frequency = <24000000>;
103 clock-names = "baudclk", "apb_pclk";
105 pinctrl-names = "default";
106 pinctrl-0 = <&uart2m0_xfer>;
111 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
114 reg-shift = <2>;
115 reg-io-width = <4>;
116 clock-frequency = <24000000>;
118 clock-names = "baudclk", "apb_pclk";
120 pinctrl-names = "default";
121 pinctrl-0 = <&uart1_xfer>;
126 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
129 reg-shift = <2>;
130 reg-io-width = <4>;
131 clock-frequency = <24000000>;
133 clock-names = "baudclk", "apb_pclk";
135 pinctrl-names = "default";
136 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
141 compatible = "rockchip,rv1108-i2c";
144 #address-cells = <1>;
145 #size-cells = <0>;
147 clock-names = "i2c", "pclk";
148 pinctrl-names = "default";
149 pinctrl-0 = <&i2c1_xfer>;
155 compatible = "rockchip,rv1108-i2c";
158 #address-cells = <1>;
159 #size-cells = <0>;
161 clock-names = "i2c", "pclk";
162 pinctrl-names = "default";
163 pinctrl-0 = <&i2c2m1_xfer>;
169 compatible = "rockchip,rv1108-i2c";
172 #address-cells = <1>;
173 #size-cells = <0>;
175 clock-names = "i2c", "pclk";
176 pinctrl-names = "default";
177 pinctrl-0 = <&i2c3_xfer>;
183 compatible = "rockchip,rv1108-spi";
187 clock-names = "spiclk", "apb_pclk";
189 dma-names = "tx", "rx";
190 #address-cells = <1>;
191 #size-cells = <0>;
196 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
199 clock-names = "pwm", "pclk";
200 pinctrl-names = "default";
201 pinctrl-0 = <&pwm4_pin>;
202 #pwm-cells = <3>;
207 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
210 clock-names = "pwm", "pclk";
211 pinctrl-names = "default";
212 pinctrl-0 = <&pwm5_pin>;
213 #pwm-cells = <3>;
218 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
221 clock-names = "pwm", "pclk";
222 pinctrl-names = "default";
223 pinctrl-0 = <&pwm6_pin>;
224 #pwm-cells = <3>;
229 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
232 clock-names = "pwm", "pclk";
233 pinctrl-names = "default";
234 pinctrl-0 = <&pwm7_pin>;
235 #pwm-cells = <3>;
239 pdma: dma-controller@102a0000 {
243 #dma-cells = <1>;
244 arm,pl330-broken-no-flushp;
245 arm,pl330-periph-burst;
247 clock-names = "apb_pclk";
251 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
253 #address-cells = <1>;
254 #size-cells = <1>;
256 io_domains: io-domains {
257 compatible = "rockchip,rv1108-io-voltage-domain";
262 compatible = "rockchip,rv1108-usb2phy";
265 clock-names = "phyclk";
266 #clock-cells = <0>;
267 clock-output-names = "usbphy";
271 u2phy_otg: otg-port {
273 interrupt-names = "otg-mux";
274 #phy-cells = <0>;
278 u2phy_host: host-port {
280 interrupt-names = "linestate";
281 #phy-cells = <0>;
288 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
292 clock-names = "pclk", "timer";
296 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
303 thermal-zones {
304 soc_thermal: soc-thermal {
305 polling-delay-passive = <20>;
306 polling-delay = <1000>;
307 sustainable-power = <50>;
308 thermal-sensors = <&tsadc 0>;
311 threshold: trip-point0 {
316 target: trip-point1 {
321 soc_crit: soc-crit {
328 cooling-maps {
331 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 compatible = "rockchip,rv1108-tsadc";
342 assigned-clocks = <&cru SCLK_TSADC>;
343 assigned-clock-rates = <750000>;
345 clock-names = "tsadc", "apb_pclk";
346 pinctrl-names = "init", "default", "sleep";
347 pinctrl-0 = <&otp_pin>;
348 pinctrl-1 = <&otp_out>;
349 pinctrl-2 = <&otp_pin>;
351 reset-names = "tsadc-apb";
352 rockchip,hw-tshut-temp = <120000>;
353 #thermal-sensor-cells = <1>;
358 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
361 #io-channel-cells = <1>;
363 clock-names = "saradc", "apb_pclk";
368 compatible = "rockchip,rv1108-i2c";
371 #address-cells = <1>;
372 #size-cells = <0>;
374 clock-names = "i2c", "pclk";
375 pinctrl-names = "default";
376 pinctrl-0 = <&i2c0_xfer>;
382 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
385 clock-names = "pwm", "pclk";
386 pinctrl-names = "default";
387 pinctrl-0 = <&pwm0_pin>;
388 #pwm-cells = <3>;
393 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
396 clock-names = "pwm", "pclk";
397 pinctrl-names = "default";
398 pinctrl-0 = <&pwm1_pin>;
399 #pwm-cells = <3>;
404 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
407 clock-names = "pwm", "pclk";
408 pinctrl-names = "default";
409 pinctrl-0 = <&pwm2_pin>;
410 #pwm-cells = <3>;
415 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
418 clock-names = "pwm", "pclk";
419 pinctrl-names = "default";
420 pinctrl-0 = <&pwm3_pin>;
421 #pwm-cells = <3>;
426 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
429 pmu_io_domains: io-domains {
430 compatible = "rockchip,rv1108-pmu-io-voltage-domain";
436 compatible = "rockchip,rv1108-usbgrf", "syscon";
440 cru: clock-controller@20200000 {
441 compatible = "rockchip,rv1108-cru";
444 clock-names = "xin24m";
446 #clock-cells = <1>;
447 #reset-cells = <1>;
450 nfc: nand-controller@30100000 {
451 compatible = "rockchip,rv1108-nfc";
455 clock-names = "ahb", "nfc";
456 assigned-clocks = <&cru SCLK_NANDC>;
457 assigned-clock-rates = <150000000>;
462 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
467 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
468 fifo-depth = <0x100>;
469 max-frequency = <150000000>;
474 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
479 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
480 fifo-depth = <0x100>;
481 max-frequency = <150000000>;
486 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
491 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
492 fifo-depth = <0x100>;
493 max-frequency = <100000000>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
500 compatible = "generic-ehci";
505 phy-names = "usb";
510 compatible = "generic-ohci";
515 phy-names = "usb";
520 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
525 clock-names = "otg";
527 g-np-tx-fifo-size = <16>;
528 g-rx-fifo-size = <280>;
529 g-tx-fifo-size = <256 128 128 64 32 16>;
531 phy-names = "usb2-phy";
540 clock-names = "clk_sfc", "hclk_sfc";
541 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
542 pinctrl-names = "default";
547 compatible = "rockchip,rv1108-gmac";
551 interrupt-names = "macirq", "eth_wake_irq";
556 clock-names = "stmmaceth",
561 phy-mode = "rmii";
562 pinctrl-names = "default";
563 pinctrl-0 = <&rmii_pins>;
568 gic: interrupt-controller@32010000 {
569 compatible = "arm,gic-400";
570 interrupt-controller;
571 #interrupt-cells = <3>;
572 #address-cells = <0>;
582 compatible = "rockchip,rv1108-pinctrl";
585 #address-cells = <1>;
586 #size-cells = <1>;
590 compatible = "rockchip,gpio-bank";
595 gpio-controller;
596 #gpio-cells = <2>;
598 interrupt-controller;
599 #interrupt-cells = <2>;
603 compatible = "rockchip,gpio-bank";
608 gpio-controller;
609 #gpio-cells = <2>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
616 compatible = "rockchip,gpio-bank";
621 gpio-controller;
622 #gpio-cells = <2>;
624 interrupt-controller;
625 #interrupt-cells = <2>;
629 compatible = "rockchip,gpio-bank";
634 gpio-controller;
635 #gpio-cells = <2>;
637 interrupt-controller;
638 #interrupt-cells = <2>;
641 pcfg_pull_up: pcfg-pull-up {
642 bias-pull-up;
645 pcfg_pull_down: pcfg-pull-down {
646 bias-pull-down;
649 pcfg_pull_none: pcfg-pull-none {
650 bias-disable;
653 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
654 drive-strength = <8>;
657 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
658 drive-strength = <12>;
661 pcfg_pull_none_smt: pcfg-pull-none-smt {
662 bias-disable;
663 input-schmitt-enable;
666 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
667 bias-pull-up;
668 drive-strength = <8>;
671 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
672 drive-strength = <4>;
675 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
676 bias-pull-up;
677 drive-strength = <4>;
680 pcfg_output_high: pcfg-output-high {
681 output-high;
684 pcfg_output_low: pcfg-output-low {
685 output-low;
688 pcfg_input_high: pcfg-input-high {
689 bias-pull-up;
690 input-enable;
694 emmc_bus8: emmc-bus8 {
705 emmc_clk: emmc-clk {
709 emmc_cmd: emmc-cmd {
715 sfc_bus4: sfc-bus4 {
723 sfc_bus2: sfc-bus2 {
729 sfc_cs0: sfc-cs0 {
734 sfc_clk: sfc-clk {
741 rmii_pins: rmii-pins {
756 i2c0_xfer: i2c0-xfer {
763 i2c1_xfer: i2c1-xfer {
770 i2c2m1_xfer: i2c2m1-xfer {
775 i2c2m1_pins: i2c2m1-pins {
782 i2c2m05v_xfer: i2c2m05v-xfer {
787 i2c2m05v_pins: i2c2m05v-pins {
794 i2c3_xfer: i2c3-xfer {
801 pwm0_pin: pwm0-pin {
807 pwm1_pin: pwm1-pin {
813 pwm2_pin: pwm2-pin {
819 pwm3_pin: pwm3-pin {
825 pwm4_pin: pwm4-pin {
831 pwm5_pin: pwm5-pin {
837 pwm6_pin: pwm6-pin {
843 pwm7_pin: pwm7-pin {
849 sdmmc_clk: sdmmc-clk {
853 sdmmc_cmd: sdmmc-cmd {
857 sdmmc_cd: sdmmc-cd {
861 sdmmc_bus1: sdmmc-bus1 {
865 sdmmc_bus4: sdmmc-bus4 {
874 spim0_clk: spim0-clk {
878 spim0_cs0: spim0-cs0 {
882 spim0_tx: spim0-tx {
886 spim0_rx: spim0-rx {
892 spim1_clk: spim1-clk {
896 spim1_cs0: spim1-cs0 {
900 spim1_rx: spim1-rx {
904 spim1_tx: spim1-tx {
910 otp_out: otp-out {
914 otp_pin: otp-pin {
920 uart0_xfer: uart0-xfer {
925 uart0_cts: uart0-cts {
929 uart0_rts: uart0-rts {
933 uart0_rts_pin: uart0-rts-pin {
939 uart1_xfer: uart1-xfer {
944 uart1_cts: uart1-cts {
948 uart1_rts: uart1-rts {
954 uart2m0_xfer: uart2m0-xfer {
961 uart2m1_xfer: uart2m1-xfer {
968 uart2_5v_cts: uart2_5v-cts {
972 uart2_5v_rts: uart2_5v-rts {