Lines Matching +full:fifo +full:- +full:depth +full:- +full:bits
4 #define TX_RING_ENTRIES 64 /* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
32 * It consists of header, 0-3 concatination
43 u64 data_len:16; /*Length of valid data in bytes-1*/
48 u64 len:16; /*length of buffer data - 1*/
91 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
99 /* Bits in METH_MAC */
110 /* Bits 5 and 6 are used to determine the Destination address filter mode */
122 … /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
126 /* Bits 15 through 21 are used to determine IPGR1 */
128 /* Bits 22 through 28 are used to determine IPGR2 */
130 #define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */
135 /* DMA control bits */
136 #define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of p…
137 #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != dept…
144 /* RX FIFO MCL Info bits */
149 /* RX status bits */
173 /* Bits in METH_INT */
183 #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could no…
184 #define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped,…
186 /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */
187 #define METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx …
189 /* Bits 13 through 15 are always 0. */
191 #define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */
193 #define METH_INT_RX_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the m…
205 /* TX status bits */
215 /* Tx command header bits */
227 #define ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1)