Lines Matching +full:fifo +full:- +full:depth +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
33 arm-pmu {
34 compatible = "arm,cortex-a7-pmu";
39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
43 #address-cells = <1>;
44 #size-cells = <0>;
45 enable-method = "rockchip,rk3036-smp";
49 compatible = "arm,cortex-a7";
53 operating-points-v2 = <&cpu_opp_table>;
54 #cooling-cells = <2>; /* min followed by max */
59 compatible = "arm,cortex-a7";
62 operating-points-v2 = <&cpu_opp_table>;
67 compatible = "arm,cortex-a7";
70 operating-points-v2 = <&cpu_opp_table>;
75 compatible = "arm,cortex-a7";
78 operating-points-v2 = <&cpu_opp_table>;
82 cpu_opp_table: opp-table-0 {
83 compatible = "operating-points-v2";
84 opp-shared;
86 opp-216000000 {
87 opp-hz = /bits/ 64 <216000000>;
88 opp-microvolt = <950000 950000 1325000>;
89 clock-latency-ns = <40000>;
91 opp-408000000 {
92 opp-hz = /bits/ 64 <408000000>;
93 opp-microvolt = <950000 950000 1325000>;
94 clock-latency-ns = <40000>;
96 opp-600000000 {
97 opp-hz = /bits/ 64 <600000000>;
98 opp-microvolt = <950000 950000 1325000>;
99 clock-latency-ns = <40000>;
101 opp-696000000 {
102 opp-hz = /bits/ 64 <696000000>;
103 opp-microvolt = <975000 975000 1325000>;
104 clock-latency-ns = <40000>;
106 opp-816000000 {
107 opp-hz = /bits/ 64 <816000000>;
108 opp-microvolt = <1075000 1075000 1325000>;
109 opp-suspend;
110 clock-latency-ns = <40000>;
112 opp-1008000000 {
113 opp-hz = /bits/ 64 <1008000000>;
114 opp-microvolt = <1200000 1200000 1325000>;
115 clock-latency-ns = <40000>;
117 opp-1200000000 {
118 opp-hz = /bits/ 64 <1200000000>;
119 opp-microvolt = <1325000 1325000 1325000>;
120 clock-latency-ns = <40000>;
124 display_subsystem: display-subsystem {
125 compatible = "rockchip,display-subsystem";
130 gpu_opp_table: opp-table-1 {
131 compatible = "operating-points-v2";
133 opp-200000000 {
134 opp-hz = /bits/ 64 <200000000>;
135 opp-microvolt = <975000 975000 1250000>;
137 opp-300000000 {
138 opp-hz = /bits/ 64 <300000000>;
139 opp-microvolt = <1050000 1050000 1250000>;
141 opp-400000000 {
142 opp-hz = /bits/ 64 <400000000>;
143 opp-microvolt = <1150000 1150000 1250000>;
145 opp-480000000 {
146 opp-hz = /bits/ 64 <480000000>;
147 opp-microvolt = <1250000 1250000 1250000>;
152 compatible = "arm,armv7-timer";
157 arm,cpu-registers-not-fw-configured;
158 clock-frequency = <24000000>;
162 compatible = "fixed-clock";
163 clock-frequency = <24000000>;
164 clock-output-names = "xin24m";
165 #clock-cells = <0>;
169 compatible = "mmio-sram";
171 #address-cells = <1>;
172 #size-cells = <1>;
175 smp-sram@0 {
176 compatible = "rockchip,rk3066-smp-sram";
182 compatible = "rockchip,rk3128-mali", "arm,mali-400";
190 interrupt-names = "gp",
197 clock-names = "bus", "core";
198 operating-points-v2 = <&gpu_opp_table>;
200 power-domains = <&power RK3128_PD_GPU>;
205 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
208 power: power-controller {
209 compatible = "rockchip,rk3128-power-controller";
210 #power-domain-cells = <1>;
211 #address-cells = <1>;
212 #size-cells = <0>;
214 power-domain@RK3128_PD_VIO {
240 #power-domain-cells = <0>;
243 power-domain@RK3128_PD_VIDEO {
251 #power-domain-cells = <0>;
254 power-domain@RK3128_PD_GPU {
258 #power-domain-cells = <0>;
263 vpu: video-codec@10106000 {
264 compatible = "rockchip,rk3128-vpu", "rockchip,rk3066-vpu";
268 interrupt-names = "vepu", "vdpu";
271 clock-names = "aclk_vdpu", "hclk_vdpu",
274 power-domains = <&power RK3128_PD_VIDEO>;
282 clock-names = "aclk", "iface";
283 power-domains = <&power RK3128_PD_VIDEO>;
284 #iommu-cells = <0>;
288 compatible = "rockchip,rk3126-vop";
293 clock-names = "aclk_vop", "dclk_vop",
297 reset-names = "axi", "ahb",
299 power-domains = <&power RK3128_PD_VIO>;
303 #address-cells = <1>;
304 #size-cells = <0>;
308 remote-endpoint = <&hdmi_in_vop>;
313 remote-endpoint = <&dsi_in_vop>;
319 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi";
323 clock-names = "pclk";
325 phy-names = "dphy";
326 power-domains = <&power RK3128_PD_VIO>;
328 reset-names = "apb";
333 #address-cells = <1>;
334 #size-cells = <0>;
340 remote-endpoint = <&vop_out_dsi>;
351 compatible = "rockchip,rk3128-qos", "syscon";
356 compatible = "rockchip,rk3128-qos", "syscon";
361 compatible = "rockchip,rk3128-qos", "syscon";
366 compatible = "rockchip,rk3128-qos", "syscon";
371 compatible = "rockchip,rk3128-qos", "syscon";
376 compatible = "rockchip,rk3128-qos", "syscon";
381 compatible = "rockchip,rk3128-qos", "syscon";
385 gic: interrupt-controller@10139000 {
386 compatible = "arm,cortex-a7-gic";
392 interrupt-controller;
393 #interrupt-cells = <3>;
394 #address-cells = <0>;
398 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
402 clock-names = "otg";
404 g-np-tx-fifo-size = <16>;
405 g-rx-fifo-size = <280>;
406 g-tx-fifo-size = <256 128 128 64 32 16>;
408 phy-names = "usb2-phy";
413 compatible = "generic-ehci";
418 phy-names = "usb";
423 compatible = "generic-ohci";
428 phy-names = "usb";
433 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
437 clock-names = "i2s_clk", "i2s_hclk";
439 dma-names = "tx", "rx";
440 #sound-dai-cells = <0>;
445 compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif";
449 clock-names = "mclk", "hclk";
451 dma-names = "tx";
452 pinctrl-names = "default";
453 pinctrl-0 = <&spdif_tx>;
454 #sound-dai-cells = <0>;
463 clock-names = "clk_sfc", "hclk_sfc";
468 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
473 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
475 dma-names = "rx-tx";
476 fifo-depth = <256>;
477 max-frequency = <150000000>;
479 reset-names = "reset";
484 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
489 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
491 dma-names = "rx-tx";
492 fifo-depth = <256>;
493 max-frequency = <150000000>;
495 reset-names = "reset";
500 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
505 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
507 dma-names = "rx-tx";
508 fifo-depth = <256>;
509 max-frequency = <150000000>;
511 reset-names = "reset";
516 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
520 clock-names = "i2s_clk", "i2s_hclk";
522 dma-names = "tx", "rx";
523 rockchip,playback-channels = <2>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2s_bus>;
526 #sound-dai-cells = <0>;
530 nfc: nand-controller@10500000 {
531 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
535 clock-names = "ahb", "nfc";
536 pinctrl-names = "default";
537 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
542 cru: clock-controller@20000000 {
543 compatible = "rockchip,rk3128-cru";
546 clock-names = "xin24m";
548 #clock-cells = <1>;
549 #reset-cells = <1>;
550 assigned-clocks = <&cru PLL_GPLL>;
551 assigned-clock-rates = <594000000>;
555 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
557 #address-cells = <1>;
558 #size-cells = <1>;
561 compatible = "rockchip,rk3128-usb2phy";
564 clock-names = "phyclk";
565 clock-output-names = "usb480m_phy";
566 assigned-clocks = <&cru SCLK_USB480M>;
567 assigned-clock-parents = <&usb2phy>;
568 #clock-cells = <0>;
571 usb2phy_host: host-port {
573 interrupt-names = "linestate";
574 #phy-cells = <0>;
578 usb2phy_otg: otg-port {
582 interrupt-names = "otg-bvalid", "otg-id",
584 #phy-cells = <0>;
591 compatible = "rockchip,rk3128-inno-hdmi";
595 clock-names = "pclk", "ref";
596 pinctrl-names = "default";
597 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
598 power-domains = <&power RK3128_PD_VIO>;
599 #sound-dai-cells = <0>;
603 #address-cells = <1>;
604 #size-cells = <0>;
609 remote-endpoint = <&vop_out_hdmi>;
620 compatible = "rockchip,rk3128-dsi-dphy";
623 clock-names = "ref", "pclk";
624 #phy-cells = <0>;
625 power-domains = <&power RK3128_PD_VIO>;
627 reset-names = "apb";
632 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
636 clock-names = "pclk", "timer";
640 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
644 clock-names = "pclk", "timer";
648 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
652 clock-names = "pclk", "timer";
656 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
660 clock-names = "pclk", "timer";
664 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
668 clock-names = "pclk", "timer";
672 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
676 clock-names = "pclk", "timer";
680 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
688 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
691 pinctrl-names = "default";
692 pinctrl-0 = <&pwm0_pin>;
693 #pwm-cells = <3>;
698 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
701 pinctrl-names = "default";
702 pinctrl-0 = <&pwm1_pin>;
703 #pwm-cells = <3>;
708 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
711 pinctrl-names = "default";
712 pinctrl-0 = <&pwm2_pin>;
713 #pwm-cells = <3>;
718 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
721 pinctrl-names = "default";
722 pinctrl-0 = <&pwm3_pin>;
723 #pwm-cells = <3>;
728 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
731 clock-names = "i2c";
733 pinctrl-names = "default";
734 pinctrl-0 = <&i2c1_xfer>;
735 #address-cells = <1>;
736 #size-cells = <0>;
741 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
744 clock-names = "i2c";
746 pinctrl-names = "default";
747 pinctrl-0 = <&i2c2_xfer>;
748 #address-cells = <1>;
749 #size-cells = <0>;
754 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
757 clock-names = "i2c";
759 pinctrl-names = "default";
760 pinctrl-0 = <&i2c3_xfer>;
761 #address-cells = <1>;
762 #size-cells = <0>;
767 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
770 clock-frequency = <24000000>;
772 clock-names = "baudclk", "apb_pclk";
774 dma-names = "tx", "rx";
775 pinctrl-names = "default";
776 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
777 reg-io-width = <4>;
778 reg-shift = <2>;
783 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
786 clock-frequency = <24000000>;
788 clock-names = "baudclk", "apb_pclk";
790 dma-names = "tx", "rx";
791 pinctrl-names = "default";
792 pinctrl-0 = <&uart1_xfer>;
793 reg-io-width = <4>;
794 reg-shift = <2>;
799 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
802 clock-frequency = <24000000>;
804 clock-names = "baudclk", "apb_pclk";
806 dma-names = "tx", "rx";
807 pinctrl-names = "default";
808 pinctrl-0 = <&uart2_xfer>;
809 reg-io-width = <4>;
810 reg-shift = <2>;
819 clock-names = "saradc", "apb_pclk";
821 reset-names = "saradc-apb";
822 #io-channel-cells = <1>;
827 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
830 clock-names = "i2c";
832 pinctrl-names = "default";
833 pinctrl-0 = <&i2c0_xfer>;
834 #address-cells = <1>;
835 #size-cells = <0>;
840 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
844 clock-names = "spiclk", "apb_pclk";
846 dma-names = "tx", "rx";
847 pinctrl-names = "default";
848 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
849 #address-cells = <1>;
850 #size-cells = <0>;
854 pdma: dma-controller@20078000 {
859 arm,pl330-broken-no-flushp;
860 arm,pl330-periph-burst;
862 clock-names = "apb_pclk";
863 #dma-cells = <1>;
867 compatible = "rockchip,rk3128-gmac";
871 interrupt-names = "macirq", "eth_wake_irq";
876 clock-names = "stmmaceth",
881 reset-names = "stmmaceth";
883 rx-fifo-depth = <4096>;
884 tx-fifo-depth = <2048>;
888 compatible = "snps,dwmac-mdio";
889 #address-cells = <0x1>;
890 #size-cells = <0x0>;
895 compatible = "rockchip,rk3128-pinctrl";
897 #address-cells = <1>;
898 #size-cells = <1>;
902 compatible = "rockchip,gpio-bank";
906 gpio-controller;
907 #gpio-cells = <2>;
908 interrupt-controller;
909 #interrupt-cells = <2>;
913 compatible = "rockchip,gpio-bank";
917 gpio-controller;
918 #gpio-cells = <2>;
919 interrupt-controller;
920 #interrupt-cells = <2>;
924 compatible = "rockchip,gpio-bank";
928 gpio-controller;
929 #gpio-cells = <2>;
930 interrupt-controller;
931 #interrupt-cells = <2>;
935 compatible = "rockchip,gpio-bank";
939 gpio-controller;
940 #gpio-cells = <2>;
941 interrupt-controller;
942 #interrupt-cells = <2>;
945 pcfg_pull_default: pcfg-pull-default {
946 bias-pull-pin-default;
949 pcfg_pull_none: pcfg-pull-none {
950 bias-disable;
954 emmc_clk: emmc-clk {
958 emmc_cmd: emmc-cmd {
962 emmc_cmd1: emmc-cmd1 {
966 emmc_pwr: emmc-pwr {
970 emmc_bus1: emmc-bus1 {
974 emmc_bus4: emmc-bus4 {
981 emmc_bus8: emmc-bus8 {
994 rgmii_pins: rgmii-pins {
1012 rmii_pins: rmii-pins {
1027 hdmii2c_xfer: hdmii2c-xfer {
1032 hdmi_hpd: hdmi-hpd {
1036 hdmi_cec: hdmi-cec {
1042 i2c0_xfer: i2c0-xfer {
1049 i2c1_xfer: i2c1-xfer {
1056 i2c2_xfer: i2c2-xfer {
1063 i2c3_xfer: i2c3-xfer {
1070 i2s_bus: i2s-bus {
1079 i2s1_bus: i2s1-bus {
1090 lcdc_dclk: lcdc-dclk {
1094 lcdc_den: lcdc-den {
1098 lcdc_hsync: lcdc-hsync {
1102 lcdc_vsync: lcdc-vsync {
1106 lcdc_rgb24: lcdc-rgb24 {
1125 flash_ale: flash-ale {
1129 flash_cle: flash-cle {
1133 flash_wrn: flash-wrn {
1137 flash_rdn: flash-rdn {
1141 flash_rdy: flash-rdy {
1145 flash_cs0: flash-cs0 {
1149 flash_dqs: flash-dqs {
1153 flash_bus8: flash-bus8 {
1166 pwm0_pin: pwm0-pin {
1172 pwm1_pin: pwm1-pin {
1178 pwm2_pin: pwm2-pin {
1184 pwm3_pin: pwm3-pin {
1190 sdio_clk: sdio-clk {
1194 sdio_cmd: sdio-cmd {
1198 sdio_pwren: sdio-pwren {
1202 sdio_bus4: sdio-bus4 {
1211 sdmmc_clk: sdmmc-clk {
1215 sdmmc_cmd: sdmmc-cmd {
1219 sdmmc_det: sdmmc-det {
1223 sdmmc_wp: sdmmc-wp {
1227 sdmmc_pwren: sdmmc-pwren {
1231 sdmmc_bus4: sdmmc-bus4 {
1240 sfc_bus2: sfc-bus2 {
1245 sfc_bus4: sfc-bus4 {
1252 sfc_clk: sfc-clk {
1256 sfc_cs0: sfc-cs0 {
1260 sfc_cs1: sfc-cs1 {
1266 spdif_tx: spdif-tx {
1272 spi0_clk: spi0-clk {
1276 spi0_cs0: spi0-cs0 {
1280 spi0_tx: spi0-tx {
1284 spi0_rx: spi0-rx {
1288 spi0_cs1: spi0-cs1 {
1292 spi1_clk: spi1-clk {
1296 spi1_cs0: spi1-cs0 {
1300 spi1_tx: spi1-tx {
1304 spi1_rx: spi1-rx {
1308 spi1_cs1: spi1-cs1 {
1312 spi2_clk: spi2-clk {
1316 spi2_cs0: spi2-cs0 {
1320 spi2_tx: spi2-tx {
1324 spi2_rx: spi2-rx {
1330 uart0_xfer: uart0-xfer {
1335 uart0_cts: uart0-cts {
1339 uart0_rts: uart0-rts {
1345 uart1_xfer: uart1-xfer {
1350 uart1_cts: uart1-cts {
1354 uart1_rts: uart1-rts {
1360 uart2_xfer: uart2-xfer {
1365 uart2_cts: uart2-cts {
1369 uart2_rts: uart2-rts {