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/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
33 DP83822 PHY in Fiber mode only.
[all …]
H A Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
21 See the respective PHY datasheet for the mode values.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
34 - clocks, clock-names: contains clocks according to the common clock bindings.
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H A Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
19 MAC, while second one is SGMII for connection to MAC or fiber.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
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H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
22 SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
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H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/linux/drivers/net/phy/
H A Dmotorcomm.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: Frank <Frank.Sae@motor-comm.com>
21 * UTP Register space | FIBER Register space
22 * ------------------------------------------------------------
23 * | UTP MII | FIBER MII |
25 * | UTP Extended | FIBER Extended |
26 * ------------------------------------------------------------
28 * ------------------------------------------------------------
104 /* FIBER Auto-Negotiation link partner ability */
125 /* TX Gig-E Delay is bits 7:4, default 0x5
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H A Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
188 /* RGMII to 1000BASE-X */
190 /* RGMII to 100BASE-FX */
390 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in marvell_config_intr()
454 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
469 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
519 * marvell,reg-init property stored in the of_node for the phydev.
521 * marvell,reg-init = <reg-page reg mask value>,...;
523 * There may be one or more sets of <reg-page reg mask value>:
525 * reg-page: which register bank to use.
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H A Dlxt.c1 // SPDX-License-Identifier: GPL-2.0+
44 /* ------------------------------------------------------------------------- */
83 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in lxt970_config_intr()
147 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in lxt971_config_intr()
206 } while (status >= 0 && retry-- && status == control); in lxt973a2_update_link()
212 phydev->link = 0; in lxt973a2_update_link()
214 phydev->link = 1; in lxt973a2_update_link()
230 if (AUTONEG_ENABLE == phydev->autoneg) { in lxt973a2_read_status()
247 } while (lpa == adv && retry--); in lxt973a2_read_status()
249 mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa); in lxt973a2_read_status()
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H A Ddp83822.c1 // SPDX-License-Identifier: GPL-2.0
109 /* SOR1 mode */
149 struct net_device *ndev = phydev->attached_dev; in dp83822_config_wol()
153 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) { in dp83822_config_wol()
154 mac = (const u8 *)ndev->dev_addr; in dp83822_config_wol()
157 return -EINVAL; in dp83822_config_wol()
171 if (wol->wolopts & WAKE_MAGIC) in dp83822_config_wol()
176 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83822_config_wol()
179 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83822_config_wol()
182 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83822_config_wol()
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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_param.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
12 #define OPTION_UNSET -1
30 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
31 * Valid Range: 80-4096 for 82544 and newer
39 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
40 * Valid Range: 80-4096 for 82544 and newer
49 * - 0 - auto-negotiate at all supported speeds
50 * - 10 - only link at 10 Mbps
51 * - 100 - only link at 100 Mbps
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/linux/drivers/net/hippi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI
12 can run over copper (25m) or fiber (300m on multi-mode or 10km on
13 single-mode). HIPPI networks are commonly used for clusters and to
/linux/drivers/net/phy/qcom/
H A Dqca807x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
40 * - With both FULL amplitude and FULL bias current: bias current
42 * - With only DSP amplitude: bias current is set to half and
44 * - With DSP bias current (included both DSP amplitude and
60 /* LED hw control pattern for fiber port */
138 switch (phydev->port) { in qca807x_led_parse_netdev()
170 return -EOPNOTSUPP; in qca807x_led_parse_netdev()
174 return -EOPNOTSUPP; in qca807x_led_parse_netdev()
184 return -EINVAL; in qca807x_led_hw_control_enable()
196 return -EINVAL; in qca807x_led_hw_is_supported()
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H A Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
23 #include <dt-bindings/net/qca-ar803x.h>
48 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
108 /* disable hibernation mode */
193 context->bmcr = phy_read(phydev, MII_BMCR); in at803x_context_save()
194 context->advertise = phy_read(phydev, MII_ADVERTISE); in at803x_context_save()
195 context->control1000 = phy_read(phydev, MII_CTRL1000); in at803x_context_save()
196 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE); in at803x_context_save()
197 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED); in at803x_context_save()
198 context->led_control = phy_read(phydev, AT803X_LED_CONTROL); in at803x_context_save()
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/linux/drivers/net/
H A Dsungem_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Add support for PHYs that provide an IRQ line
11 * - Eventually moved the entire polling state machine in
14 * - On LXT971 & BCM5201, Apple uses some chip specific regs
17 * - Apple has some additional power management code for some
49 return phy->mdio_read(phy->dev, id, reg); in __sungem_phy_read()
54 phy->mdio_write(phy->dev, id, reg, val); in __sungem_phy_write()
59 return phy->mdio_read(phy->dev, phy->mii_id, reg); in sungem_phy_read()
64 phy->mdio_write(phy->dev, phy->mii_id, reg, val); in sungem_phy_write()
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/linux/Documentation/networking/device_drivers/ethernet/intel/
H A De1000e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
82 - 0: Off
86 - 1: Dynamic mode
[all …]
H A De1000.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999 - 2013 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Speed and Duplex Configuration
16 - Additional Configurations
17 - Support
50 -------
54 :Valid Range: 0x01-0x0F, 0x20-0x2F
57 This parameter is a bit-mask that specifies the speed and duplex settings
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * e1000e_get_bus_info_pcie - Get PCIe bus information
18 struct pci_dev *pdev = hw->adapter->pdev; in e1000e_get_bus_info_pcie()
19 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
20 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
24 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
27 bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW, in e1000e_get_bus_info_pcie()
31 mac->ops.set_lan_id(hw); in e1000e_get_bus_info_pcie()
37 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
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H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
[all …]
/linux/drivers/atm/
H A Dfore200e.h1 /* SPDX-License-Identifier: GPL-2.0 */
52 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE)…
56 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
61 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
65 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
66 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
256 OPCODE_SET_OC3, /* set OC-3 registers */
257 OPCODE_GET_OC3, /* get OC-3 registers */
318 /* OC-3 registers */
321 u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite
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/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h1 /* SPDX-License-Identifier: GPL-2.0-only */
190 #define WFCR_SLEEP BIT(4) /* Enable sleep mode */
191 #define WFCR_WAKEUP BIT(5) /* Enable wakeup mode */
207 #define PSCR_FPS BIT(3) /* Enable fiber mode PS */
215 #define PSCR_FOF BIT(9) /* Force PHY in fiber mode */
232 #define MACCR_PSI BIT(6) /* Software Cable-Off */
529 /* bit 15-11: flags, bit 10-0: packet length */
531 /* bit 15-11: sequence number, bit 11-0: packet length bar */
536 /* bit 15-14: flags, bit 13-11: segment number */
537 /* bit 10-0: segment length */
[all …]
/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_mac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
57 switch (mac_cb->max_speed) { in hns_get_enet_interface()
59 return g_mac_mode_100[mac_cb->phy_if]; in hns_get_enet_interface()
61 return g_mac_mode_1000[mac_cb->phy_if]; in hns_get_enet_interface()
77 if (!mac_ctrl_drv->get_link_status) in hns_mac_link_anti_shake()
82 mac_ctrl_drv->get_link_status(mac_ctrl_drv, &link_status); in hns_mac_link_anti_shake()
97 if (mac_ctrl_drv->get_link_status) in hns_mac_get_link_status()
98 mac_ctrl_drv->get_link_status(mac_ctrl_drv, link_status); in hns_mac_get_link_status()
102 if (mac_cb->media_type == HNAE_MEDIA_TYPE_FIBER) { in hns_mac_get_link_status()
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/linux/drivers/scsi/bfa/
H A Dbfa_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */
102 * All numerical fields are in big-endian format.
125 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists,
129 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */
132 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */
148 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz8.c1 // SPDX-License-Identifier: GPL-2.0
6 * - KSZ8863, KSZ8873 aka KSZ88X3
7 * - KSZ8895, KSZ8864 aka KSZ8895 family
8 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX
10 * - KSZ8563, KSZ8567 - see KSZ9477 driver
23 #include <linux/platform_data/microchip-ksz.h>
49 * ksz8_ind_write8 - EEE/ACL/PME indirect register write
56 * PME switch functionalities. Both 8-bit registers 110 and 111 are
68 regs = dev->info->regs; in ksz8_ind_write8()
70 mutex_lock(&dev->alu_mutex); in ksz8_ind_write8()
[all …]
/linux/drivers/net/fddi/
H A Ddefza.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
36 #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
43 #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
45 * unsupported partial-word accesses
93 #define FZA_HALT_HOST 0x01 /* host-directed HALT */
95 #define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
102 #define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
106 #define FZA_TEST_SRAM_STUCK1 0x04 /* SRAM stuck-at range 1 */
107 #define FZA_TEST_SRAM_STUCK2 0x05 /* SRAM stuck-at range 2 */
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