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Searched +full:enable +full:- +full:soft +full:- +full:reset (Results 1 – 25 of 249) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
18 reset control registers.
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
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/freebsd/sys/arm/freescale/imx/
H A Dimx_wdogreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #define WDOG_CR_WDA (1u << 5) /* Don't assert ext reset */
38 #define WDOG_CR_SRS (1u << 4) /* Don't assert soft reset */
39 #define WDOG_CR_WDT (1u << 3) /* Assert ext reset on timeout */
40 #define WDOG_CR_WDE (1u << 2) /* Watchdog Enable */
48 #define WDOG_RSR_REG 0x04 /* Reset Status Register */
49 #define WDOG_RSR_POR (1u << 4) /* Due to Power-On Reset */
50 #define WDOG_RSR_TOUT (1u << 1) /* Due WDog timeout reset */
51 #define WDOG_RSR_SFTW (1u << 0) /* Due Soft reset */
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dhisilicon,histb-xhci.txt6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
19 "soft": for soft reset
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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dimg,pistachio-reset.txt1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
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/freebsd/share/man/man9/
H A Diflibdd.99 .Ss "Soft Queue Setup and Teardown Functions"
122 .Ss "Interrupt enable/disable"
194 .Ss Soft Queue Setup and Teardown
195 .Bl -ohang -offset indent
221 .Bl -ohang -offset indent
244 .Bl -ohang -offset indent
247 For example, it will reset the chip and enable the receiver unit.
253 a global reset on the MAC and deallocating the TX and RX buffers.
260 The driver sets the appropriate link type and speed in ifmr->ifm_active.
281 .Ss Interrupt Enable/Disable
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/freebsd/share/misc/
H A Dusb_hid_usages4 # - lines that do not start with a white space give the number and name of
6 # - lines that start with a white space give the number and name of
20 0x08 Multi-axis Controller
62 0x90 D-pad Up
63 0x91 D-pad Down
64 0x92 D-pad Right
65 0x93 D-pad Left
107 0xB2 Anti-Torque Control
108 0xB3 Autopilot Enable
151 0x20 Stereo Enable
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/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsahw.c2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
24 * \brief The file implements the functions for reset and shutdown
73 /*! \brief Function to reset the Hardware
75 * The saHwReset() function is called to reset the SAS/SATA HW controller
80 * \param resetType The reset type
81 * \param resetParm The paramter passed for reset operation
83 * \return -void-
103 DbgPrint("Reset Start\n"); in saHwReset()
112 if (agNULL != agRoot->sdkData) in saHwReset()
114 saRoot = (agsaLLRoot_t*) agRoot->sdkData; in saHwReset()
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/freebsd/sys/arm/ti/am335x/
H A Dam335x_dmtreg.h1 /*-
34 #define DMT_TIOCP_RESET (1 << 0) /* TIOCP perform soft reset */
35 #define DMT_IQR_EOI 0x20 /* IRQ End-Of-Interrupt Reg */
40 #define DMT_IRQWAKEEN 0x34 /* IRQ Wakeup Enable Reg */
47 #define DMT_TCLR_AUTOLOAD (1 << 1) /* Auto-reload on overflow */
49 #define DMT_TCLR_PRES_ENABLE (1 << 5) /* Prescaler enable */
50 #define DMT_TCLR_COMP_ENABLE (1 << 6) /* Compare enable */
54 #define DMT_TCLR_CAPTRAN_LOHI (1 << 8) /* Capture lo->hi transition */
55 #define DMT_TCLR_CAPTRAN_HILO (2 << 8) /* Capture hi->lo transition */
71 #define DMT_TSICR_RESET (1 << 1) /* TSICR perform soft reset */
/freebsd/sys/dev/usb/net/
H A Dif_muge.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 * USB-To-Ethernet adapter driver for Microchip's LAN78XX and related families.
42 * USB 2 to 10/100/1000 Mbps Ethernet with built-in USB hub
45 * This driver is based on the if_smsc driver, with lan78xx-specific
49 * -
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H A Dif_smsc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * Microchip LAN9xxx devices (https://www.microchip.com/en-us/product/lan9500a)
33 * The LAN9500 & LAN9500A devices are stand-alone USB to Ethernet chips that
47 * ---------------------------------
52 * the Ethernet frame, this means if the frame is padded with non-zero values
167 device_printf((sc)->sc_ue.ue_dev, "debug: " fmt, ##args); \
174 device_printf((sc)->sc_ue.ue_dev, "warning: " fmt, ##args)
177 device_printf((sc)->sc_ue.ue_dev, "error: " fmt, ##args)
252 * smsc_read_reg - Reads a 32-bit register on the device
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dcs4271.txt7 - compatible: "cirrus,cs4271"
10 Documentation/devicetree/bindings/spi/spi-bus.txt
14 - reg: the i2c address
19 - reset-gpio: a GPIO spec to define which pin is connected to the chip's
20 !RESET pin
21 - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
23 - cirrus,enable-soft-reset:
24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
25 line is de-asserted. That also means that clocks cannot be changed
26 without putting the chip back into hardware reset, which also requires
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H A Dcirrus,cs4271.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
18 - $ref: dai-common.yaml#
19 - $ref: /schemas/spi/spi-peripheral-props.yaml#
28 spi-cpha: true
30 spi-cpol: true
32 '#sound-dai-cells':
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H A Dcs35l33.txt5 - compatible : "cirrus,cs35l33"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
15 - reset-gpios : gpio used to reset the amplifier
17 - interrupts : IRQ line info CS35L33.
18 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
26 - cirrus,ramp-rate : On power up, it affects the time from when the power
27 up sequence begins to the time the audio reaches a full-scale output.
28 On power down, it affects the time from when the power-down sequence
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/freebsd/sys/dev/liquidio/base/
H A Dcn23xx_pf_device.c50 lio_dev_dbg(oct, "BIST enabled for CN23XX soft reset\n"); in lio_cn23xx_pf_soft_reset()
54 /* Initiate chip-wide soft reset */ in lio_cn23xx_pf_soft_reset()
62 lio_dev_err(oct, "Soft reset failed\n"); in lio_cn23xx_pf_soft_reset()
66 lio_dev_dbg(oct, "Reset completed\n"); in lio_cn23xx_pf_soft_reset()
68 /* restore the reset value */ in lio_cn23xx_pf_soft_reset()
89 lio_dev_err(oct, "PCI-E Fatal error detected;\n" in lio_cn23xx_pf_enable_error_reporting()
97 regval |= 0xf; /* Enable Link error reporting */ in lio_cn23xx_pf_enable_error_reporting()
99 lio_dev_dbg(oct, "Enabling PCI-E error reporting..\n"); in lio_cn23xx_pf_enable_error_reporting()
111 /* TBD: get the info in Hand-shake */ in lio_cn23xx_pf_coprocessor_clock()
121 oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us; in lio_cn23xx_pf_get_oq_ticks()
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/freebsd/share/doc/smm/04.quotas/
H A Dquotas.ms28 .EH 'SMM:4-%''Disc Quotas in a \s-2UNIX\s+2 Environment'
29 .OH 'Disc Quotas in a \s-2UNIX\s+2 Environment''SMM:4-%'
32 Disc Quotas in a \s-2UNIX\s+2\s-3\u*\d\s0 Environment
62 \s-2VMUNIX\s0 that may be included when the
87 usage, soft limit (quota), hard limit, and number
89 The soft limit is the number of 1K blocks (or files)
105 his soft limit, he will be warned, and his login
107 When he logs in under quota, the counter is reset
115 The \fBonly\fP way to reset this condition is
156 the disc quota sub-system.
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/freebsd/usr.sbin/bhyve/amd64/
H A Dpm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
54 * Reset Control register at I/O port 0xcf9. Bit 2 forces a system
55 * reset when it transitions from 0 to 1. Bit 1 selects the type of
56 * reset to attempt: 0 selects a "soft" reset, and 1 selects a "hard"
57 * reset.
68 return (-1); in reset_handler()
74 /* Treat hard and soft resets the same. */ in reset_handler()
85 * ACPI's SCI is a level-triggered interrupt.
163 return (-1); in pm1_status_handler()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
35 BranchRelaxation("sparc-enable-branch-relax", cl::Hidden, cl::init(true),
41 Ret += "-m:e"; in computeDataLayout()
45 Ret += "-p:32:32"; in computeDataLayout()
48 Ret += "-i64:64"; in computeDataLayout()
53 Ret += "-n32:64"; in computeDataLayout()
55 Ret += "-f128:64-n32"; in computeDataLayout()
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/freebsd/sys/arm/ti/
H A Dti_wdt.h1 /*-
34 #define TI_WDT_WIER 0x1c /* Watchdog Interrupt Enable Register */
44 #define TI_WDT_WIRQENSET 0x5c /* Watchdog Int. Enable Set Register */
45 #define TI_WDT_WIRQENCLR 0x60 /* Watchdog Int. Enable Clear Reg. */
48 #define TI_WDSC_SR (1 << 1) /* Soft reset */
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_dcu4.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
137 #define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */
148 #define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */
149 #define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */
150 #define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */
151 #define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */
152 #define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */
153 #define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */
154 #define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */
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/freebsd/sys/dev/sound/pci/
H A Denvy24.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
49 #define PCIM_LAC_GAME 0x0004 /* Game Port enable (200h) */
50 #define PCIM_LAC_FM 0x0002 /* FM I/O enable (AdLib 388h base) */
51 #define PCIM_LAC_SB 0x0001 /* SB I/O enable */
55 #define PCIM_LCC_SVIDRW 0x0080 /* SVID read/write enable */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
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/freebsd/sys/dev/xilinx/
H A Daxidma.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
38 #define DMACR_RESET (1 << 2) /* Soft reset the AXI DMA core. */
39 #define DMACR_IOC_IRQEN (1 << 12) /* Interrupt on Complete (IOC) Interrupt Enable. */
40 #define DMACR_DLY_IRQEN (1 << 13) /* Interrupt on Delay Timer Interrupt Enable. */
41 #define DMACR_ERR_IRQEN (1 << 14) /* Interrupt on Error Interrupt Enable. */
/freebsd/sys/dev/mrsas/
H A Dmrsas.c205 {0x1000, MRSAS_AERO_10E0, 0xffff, 0xffff, "BROADCOM AERO-10E0 SAS Controller"},
206 {0x1000, MRSAS_AERO_10E1, 0xffff, 0xffff, "BROADCOM AERO-10E1 SAS Controller"},
207 {0x1000, MRSAS_AERO_10E2, 0xffff, 0xffff, "BROADCOM AERO-10E2 SAS Controller"},
208 {0x1000, MRSAS_AERO_10E3, 0xffff, 0xffff, "BROADCOM AERO-10E3 SAS Controller"},
209 {0x1000, MRSAS_AERO_10E4, 0xffff, 0xffff, "BROADCOM AERO-10E4 SAS Controller"},
210 {0x1000, MRSAS_AERO_10E5, 0xffff, 0xffff, "BROADCOM AERO-10E5 SAS Controller"},
211 {0x1000, MRSAS_AERO_10E6, 0xffff, 0xffff, "BROADCOM AERO-10E6 SAS Controller"},
212 {0x1000, MRSAS_AERO_10E7, 0xffff, 0xffff, "BROADCOM AERO-10E7 SAS Controller"},
250 if (sc->is_aero) { in mrsas_read_reg_with_retries()
269 bus_space_tag_t bus_tag = sc->bus_tag; in mrsas_write_reg()
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/freebsd/sys/arm/arm/
H A Dcpufunc.c3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
86 /* Soft functions */
109 /* Soft functions */
181 arm_dcache_align_mask = arm_dcache_align - 1; in get_cachetype_cp15()
254 * Set PMCR[2,0] to enable counters and reset CCNT in cpu_scc_setup_ccnt()
255 * Set PMCNTENSET to 0x80000000 to enable CCNT */ in cpu_scc_setup_ccnt()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetMachine.cpp1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
34 "systemz-machine-combiner",
35 cl::desc("Enable the machine combiner pass"),
38 // NOLINTNEXTLINE(readability-identifier-naming)
65 Ret += "-i1:8:16-i8:8:16"; in computeDataLayout()
67 // 64-bit integers are naturally aligned. in computeDataLayout()
68 Ret += "-i64:64"; in computeDataLayout()
70 // 128-bit floats are aligned only to 64 bits. in computeDataLayout()
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/freebsd/sys/arm/allwinner/
H A Dif_emacreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
103 * Byte 1: 0x43 -> Ascii code 'C'
104 * Byte 2: 0x41 -> Ascii code 'A'
105 * Byte 3: 0x4d -> Ascii code 'M'
113 /* Aborted frame enable */
116 /* 0: Enable CPU mode for TX, 1: DMA */
122 /* 0: Enable CPU mode for RX, 1: DMA */
143 /* Enable DA Filtering */
149 /* Enable Hash filter */
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