1*2ffc65f9SRui Paulo /*- 2*2ffc65f9SRui Paulo * Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org> 3*2ffc65f9SRui Paulo * All rights reserved. 4*2ffc65f9SRui Paulo * 5*2ffc65f9SRui Paulo * Redistribution and use in source and binary forms, with or without 6*2ffc65f9SRui Paulo * modification, are permitted provided that the following conditions 7*2ffc65f9SRui Paulo * are met: 8*2ffc65f9SRui Paulo * 1. Redistributions of source code must retain the above copyright 9*2ffc65f9SRui Paulo * notice, this list of conditions and the following disclaimer. 10*2ffc65f9SRui Paulo * 2. Redistributions in binary form must reproduce the above copyright 11*2ffc65f9SRui Paulo * notice, this list of conditions and the following disclaimer in the 12*2ffc65f9SRui Paulo * documentation and/or other materials provided with the distribution. 13*2ffc65f9SRui Paulo * 14*2ffc65f9SRui Paulo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15*2ffc65f9SRui Paulo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16*2ffc65f9SRui Paulo * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17*2ffc65f9SRui Paulo * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18*2ffc65f9SRui Paulo * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19*2ffc65f9SRui Paulo * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20*2ffc65f9SRui Paulo * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21*2ffc65f9SRui Paulo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22*2ffc65f9SRui Paulo * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23*2ffc65f9SRui Paulo * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24*2ffc65f9SRui Paulo * POSSIBILITY OF SUCH DAMAGE. 25*2ffc65f9SRui Paulo */ 26*2ffc65f9SRui Paulo #ifndef _TI_WDT_H_ 27*2ffc65f9SRui Paulo #define _TI_WDT_H_ 28*2ffc65f9SRui Paulo 29*2ffc65f9SRui Paulo /* TI WDT registers */ 30*2ffc65f9SRui Paulo #define TI_WDT_WIDR 0x00 /* Watchdog Identification Register */ 31*2ffc65f9SRui Paulo #define TI_WDT_WDSC 0x10 /* Watchdog System Control Register */ 32*2ffc65f9SRui Paulo #define TI_WDT_WDST 0x14 /* Watchdog Status Register */ 33*2ffc65f9SRui Paulo #define TI_WDT_WISR 0x18 /* Watchdog Interrupt Status Register */ 34*2ffc65f9SRui Paulo #define TI_WDT_WIER 0x1c /* Watchdog Interrupt Enable Register */ 35*2ffc65f9SRui Paulo #define TI_WDT_WCLR 0x24 /* Watchdog Control Register */ 36*2ffc65f9SRui Paulo #define TI_WDT_WCRR 0x28 /* Watchdog Counter Register */ 37*2ffc65f9SRui Paulo #define TI_WDT_WLDR 0x2c /* Watchdog Load Register */ 38*2ffc65f9SRui Paulo #define TI_WDT_WTGR 0x30 /* Watchdog Trigger Register */ 39*2ffc65f9SRui Paulo #define TI_WDT_WWPS 0x34 /* Watchdog Write Posting Register */ 40*2ffc65f9SRui Paulo #define TI_WDT_WDLY 0x44 /* Watchdog Delay Configuration Reg */ 41*2ffc65f9SRui Paulo #define TI_WDT_WSPR 0x48 /* Watchdog Start/Stop Register */ 42*2ffc65f9SRui Paulo #define TI_WDT_WIRQSTATRAW 0x54 /* Watchdog Raw Interrupt Status Reg. */ 43*2ffc65f9SRui Paulo #define TI_WDT_WIRQSTAT 0x58 /* Watchdog Int. Status Register */ 44*2ffc65f9SRui Paulo #define TI_WDT_WIRQENSET 0x5c /* Watchdog Int. Enable Set Register */ 45*2ffc65f9SRui Paulo #define TI_WDT_WIRQENCLR 0x60 /* Watchdog Int. Enable Clear Reg. */ 46*2ffc65f9SRui Paulo 47*2ffc65f9SRui Paulo /* WDT_WDSC Register */ 48*2ffc65f9SRui Paulo #define TI_WDSC_SR (1 << 1) /* Soft reset */ 49*2ffc65f9SRui Paulo 50*2ffc65f9SRui Paulo /* 51*2ffc65f9SRui Paulo * WDT_WWPS Register 52*2ffc65f9SRui Paulo * 53*2ffc65f9SRui Paulo * Writes to some registers require synchronisation with a different clock 54*2ffc65f9SRui Paulo * domain. The WDT_WWPS register is the place where this synchronisation 55*2ffc65f9SRui Paulo * happens. 56*2ffc65f9SRui Paulo */ 57*2ffc65f9SRui Paulo #define TI_W_PEND_WCLR (1 << 0) 58*2ffc65f9SRui Paulo #define TI_W_PEND_WCRR (1 << 1) 59*2ffc65f9SRui Paulo #define TI_W_PEND_WLDR (1 << 2) 60*2ffc65f9SRui Paulo #define TI_W_PEND_WTGR (1 << 3) 61*2ffc65f9SRui Paulo #define TI_W_PEND_WSPR (1 << 4) 62*2ffc65f9SRui Paulo #define TI_W_PEND_WDLY (1 << 5) 63*2ffc65f9SRui Paulo 64*2ffc65f9SRui Paulo /* WDT_WIRQENSET Register */ 65*2ffc65f9SRui Paulo #define TI_IRQ_EN_OVF (1 << 0) /* Overflow interrupt */ 66*2ffc65f9SRui Paulo #define TI_IRQ_EN_DLY (1 << 1) /* Delay interrupt */ 67*2ffc65f9SRui Paulo 68*2ffc65f9SRui Paulo /* WDT_WIRQSTAT Register */ 69*2ffc65f9SRui Paulo #define TI_IRQ_EV_OVF (1 << 0) /* Overflow event */ 70*2ffc65f9SRui Paulo #define TI_IRQ_EV_DLY (1 << 1) /* Delay event */ 71*2ffc65f9SRui Paulo 72*2ffc65f9SRui Paulo #endif /* _TI_WDT_H_ */ 73