Lines Matching +full:enable +full:- +full:soft +full:- +full:reset
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
49 #define PCIM_LAC_GAME 0x0004 /* Game Port enable (200h) */
50 #define PCIM_LAC_FM 0x0002 /* FM I/O enable (AdLib 388h base) */
51 #define PCIM_LAC_SB 0x0001 /* SB I/O enable */
55 #define PCIM_LCC_SVIDRW 0x0080 /* SVID read/write enable */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
61 #define PCIM_LCC_LDMA 0x0001 /* Legacy DMA enable */
68 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */
71 #define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */
72 #define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
74 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */
75 #define PCIM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
99 #define ENVY24_CCS_CTL_RESET 0x80 /* Entire Chip soft reset */
100 #define ENVY24_CCS_CTL_DMAINT 0x40 /* DS DMA Channel-C interrupt */
110 #define ENVY24_CCS_IMASK_PMT 0x10 /* Professional Multi-track */
120 #define ENVY24_CCS_ISTAT_PMT 0x10 /* Professional Multi-track */
142 #define ENVY24_CCS_AC97CMD_COLD 0x80 /* Cold reset */
143 #define ENVY24_CCS_AC97CMD_WARM 0x40 /* Warm reset */
190 #define ENVY24_CCS_TIMER_EN 0x8000 /* Timer count enable */
206 #define ENVY24_CCI_PCTL_ENABLE 0x01 /* Playback enable */
212 #define ENVY24_CCI_SOFTVOL 0x05 /* Soft Volume/Mute Control Register */
220 #define ENVY24_CCI_RCTL_DRTN 0x80 /* Digital return enable */
225 #define ENVY24_CCI_RCTL_ENABLE 0x01 /* Record enable */
243 #define ENVY24_CCI_MTPDWN 0x31 /* Multi-Track Section Power Down Register */
247 #define ENVY24_CCI_MTPDWN_I2S 0x01 /* Multi-track I2S serial interface clock */
251 #define ENVY24_DDMA_ADDR0 0x00 /* DMA Base and Current Address bit 0-7 */
252 #define ENVY24_DDMA_ADDR8 0x01 /* DMA Base and Current Address bit 8-15 */
253 #define ENVY24_DDMA_ADDR16 0x02 /* DMA Base and Current Address bit 16-23 */
254 #define ENVY24_DDMA_ADDR24 0x03 /* DMA Base and Current Address bit 24-31 */
255 #define ENVY24_DDMA_CNT0 0x04 /* DMA Base and Current Count 0-7 */
256 #define ENVY24_DDMA_CNT8 0x05 /* DMA Base and Current Count 8-15 */
260 #define ENVY24_DDMA_RESET 0x0c /* Master reset */
280 #define ENVY24_CS_CTL_AUTO1 0x40 /* Buffer_1 auto init. enable */
281 #define ENVY24_CS_CTL_AUTO0 0x20 /* Buffer_0 auto init. enable */
284 #define ENVY24_CS_CTL_U8 0x04 /* 8-bit unsigned(or 16-bit signed) */
291 /* Professional Multi-Track Control Registers */
294 #define ENVY24_MT_INT_RMASK 0x80 /* Multi-track record interrupt mask */
295 #define ENVY24_MT_INT_PMASK 0x40 /* Multi-track playback interrupt mask */
296 #define ENVY24_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */
297 #define ENVY24_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */
324 #define ENVY24_MT_AC97CMD_CLD 0x80 /* Cold reset */
325 #define ENVY24_MT_AC97CMD_WRM 0x40 /* Warm reset */
329 #define ENVY24_MT_AC97CMD_ID 0x03 /* ID(0-3) for external AC 97 registers */
364 /* -------------------------------------------------------------------- */
391 #define ENVY24_VOL_MIN 96 /* -144db(negate) */
394 /* -------------------------------------------------------------------- */
398 ENVY24 has input->output data routing matrix switch. But original ENVY24
406 (NOTICE: this class is able to set only DAC-1 and S/PDIF output)
437 /* -------------------------------------------------------------------- */
462 /* GPIO connect map of M-Audio Delta series */
472 /* M-Audio Delta series S/PDIF(CS84[01]4) control pin values */
478 /* M-Audio Delta series parameter */