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/linux/Documentation/devicetree/bindings/opp/
H A Dti,omap-opp-supply.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/ti,omap-opp-supply.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 OMAP5, DRA7, and AM57 families of SoCs have Class 0 AVS eFuse
11 registers, which contain OPP-specific voltage information tailored
16 Also, some supplies may have an associated vbb-supply, an Adaptive
18 w.r.t the vdd-supply and clk when making an OPP transition. By
20 transitions, we can use the multi-regulator support implemented by
22 OPP core binding Documentation/devicetree/bindings/opp/opp-v2.yaml
[all …]
/linux/drivers/opp/
H A Dti-opp-supply.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
5 * Dave Gerlach <d-gerlach@ti.com>
26 * struct ti_opp_supply_optimum_voltage_table - optimized voltage table
28 * @optimized_uv: Optimized voltage from efuse
36 * struct ti_opp_supply_data - OMAP specific opp supply data
54 * struct ti_opp_supply_of_data - device tree match data
56 * @efuse_voltage_mask: mask required for efuse register representing voltage
57 * @efuse_voltage_uv: Are the efuse entries in micro-volts? if not, assume
58 * milli-volts.
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-pcie.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/nvmem-consumer.h>
15 #include "phy-mtk-io.h"
36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
50 * struct mtk_pcie_phy_data - phy data for each SoC
52 * @sw_efuse_supported: support software to load eFuse data
60 * struct mtk_pcie_phy - PCIe phy driver main structure
65 * @sw_efuse_en: software eFuse enable status
67 * @efuse: pointer to eFuse data for each lane
[all …]
/linux/drivers/nvmem/
H A Dqfprom.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/nvmem-provider.h>
23 /* Amount of time required to hold charge to blow fuse in micro-seconds */
44 * struct qfprom_soc_data - config that varies from SoC to SoC.
47 * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
50 * @qfprom_blow_uV: LDO voltage to be set when doing efuse blow
60 * struct qfprom_priv - structure holding qfprom attributes
62 * @qfpraw: iomapped memory space for qfprom-efuse raw address space.
63 * @qfpconf: iomapped memory space for qfprom-efuse configuration address
84 * struct qfprom_touched_values - saved values to restore after blowing
[all …]
/linux/Documentation/devicetree/bindings/nvmem/
H A Dmicrochip,sama7g5-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
15 settings, chip identifiers) or user specific data could be stored.
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
24 - const: microchip,sama7g5-otpc
25 - const: syscon
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 target-module@42c01900 {
13 compatible = "ti,sysc-dra7-mcan", "ti,sysc";
15 #address-cells = <1>;
16 #size-cells = <1>;
20 reg-names = "rev", "sysc", "syss";
21 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
23 ti,syss-mask = <1>;
25 clock-names = "fck";
[all …]
/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8723b.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8723b specific subdriver
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
238 * they never actually check the package type - and just default
293 struct device *dev = &priv->udev->dev; in rtl8723bu_identify_chip()
298 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8723bu_identify_chip()
301 ret = -ENOTSUPP; in rtl8723bu_identify_chip()
305 strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name)); in rtl8723bu_identify_chip()
306 priv->rtl_chip = RTL8723B; in rtl8723bu_identify_chip()
[all …]
H A D8192e.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8192e specific subdriver
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
467 struct device *dev = &priv->udev->dev; in rtl8192eu_identify_chip()
472 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8192eu_identify_chip()
475 ret = -ENOTSUPP; in rtl8192eu_identify_chip()
482 strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
483 priv->tx_paths = 1; in rtl8192eu_identify_chip()
484 priv->rtl_chip = RTL8191E; in rtl8192eu_identify_chip()
[all …]
H A D8192f.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8192fu specific subdriver
8 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
11 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
394 struct device *dev = &priv->udev->dev; in rtl8192fu_identify_chip()
397 strscpy(priv->chip_name, "8192FU", sizeof(priv->chip_name)); in rtl8192fu_identify_chip()
398 priv->rtl_chip = RTL8192F; in rtl8192fu_identify_chip()
399 priv->rf_paths = 2; in rtl8192fu_identify_chip()
400 priv->rx_paths = 2; in rtl8192fu_identify_chip()
401 priv->tx_paths = 2; in rtl8192fu_identify_chip()
[all …]
H A D8188f.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8188f specific subdriver
8 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
11 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
310 struct device *dev = &priv->udev->dev; in rtl8188fu_identify_chip()
314 strscpy(priv->chip_name, "8188FU", sizeof(priv->chip_name)); in rtl8188fu_identify_chip()
315 priv->rtl_chip = RTL8188F; in rtl8188fu_identify_chip()
316 priv->rf_paths = 1; in rtl8188fu_identify_chip()
317 priv->rx_paths = 1; in rtl8188fu_identify_chip()
318 priv->tx_paths = 1; in rtl8188fu_identify_chip()
[all …]
H A D8710b.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8710bu aka 8188gu specific subdriver
8 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
11 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
465 struct device *dev = &priv->udev->dev; in rtl8710b_indirect_read32()
475 mutex_lock(&priv->syson_indirect_access_mutex); in rtl8710b_indirect_read32()
482 while ((val32 & BIT(31)) && (--polling_count > 0)); in rtl8710b_indirect_read32()
490 mutex_unlock(&priv->syson_indirect_access_mutex); in rtl8710b_indirect_read32()
500 struct device *dev = &priv->udev->dev; in rtl8710b_indirect_write32()
510 mutex_lock(&priv->syson_indirect_access_mutex); in rtl8710b_indirect_write32()
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dthead,th1520-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-Head TH1520 SoC pin controller
10 - Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC.
17 PADCTRL_AOSYS -> PAD Group 1
18 PADCTRL1_APSYS -> PAD Group 2
19 PADCTRL0_APSYS -> PAD Group 3
[all …]
/linux/drivers/regulator/
H A Dti-abb-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2012-2013 Texas Instruments, Inc.
26 * FAST_OPP: sets ABB LDO to Forward Body-Bias
27 * SLOW_OPP: sets ABB LDO to Reverse Body-Bias
34 * struct ti_abb_info - ABB information per voltage setting
47 * struct ti_abb_reg - Register description for ABB block
50 * @sr2_wtcnt_value_mask: setup register- sr2_wtcnt_value mask
51 * @fbb_sel_mask: setup register- FBB sel mask
52 * @rbb_sel_mask: setup register- RBB sel mask
53 * @sr2_en_mask: setup register- enable mask
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
46 return skb->priority; in rtw_pci_get_tx_qsel()
52 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
54 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
59 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read16()
61 return readw(rtwpci->mmap + addr); in rtw_pci_read16()
66 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read32()
68 return readl(rtwpci->mmap + addr); in rtw_pci_read32()
73 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_write8()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c107 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
121 /* De-assert reset */ in fiji_start_smu_in_protection_mode()
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
130 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
134 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
147 if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
150 "SMU Firmware start failed!", return -1); in fiji_start_smu_in_protection_mode()
169 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_non_protection_mode()
[all …]
H A Dvegam_smumgr.c88 return -ENOMEM; in vegam_smu_init()
90 hwmgr->smu_backend = smu_data; in vegam_smu_init()
94 return -EINVAL; in vegam_smu_init()
108 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); in vegam_start_smu_in_protection_mode()
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
121 /* De-assert reset */ in vegam_start_smu_in_protection_mode()
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
137 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
139 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); in vegam_start_smu_in_protection_mode()
[all …]
H A Dpolaris10_smumgr.c99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); in polaris10_perform_btc()
101 if (0 != smu_data->avfs_btc_param) { in polaris10_perform_btc()
102 …if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param, in polaris10_perform_btc()
105 result = -1; in polaris10_perform_btc()
108 if (smu_data->avfs_btc_param > 1) { in polaris10_perform_btc()
109 /* Soft-Reset to reset the engine before loading uCode */ in polaris10_perform_btc()
111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in polaris10_perform_btc()
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in polaris10_perform_btc()
135 return -1); in polaris10_setup_graphics_level_structure()
[all …]
/linux/include/linux/habanalabs/
H A Dhl_boot_if.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2023 HabanaLabs, Ltd.
11 #define LKD_HARD_RESET_MAGIC 0xED7BD694 /* deprecated - do not use */
47 * will clear the non-relevant ones.
89 * started, but is not ready yet - chip
97 * CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed.
114 * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one
124 * CPU_BOOT_ERR0_BINNING_FAIL Binning settings failed, meaning
226 * Initialized in: u-boot
231 * Initialized in: u-boot
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dhw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
5 #include "../efuse.h"
27 *((u32 *) (val)) = rtlpci->receive_config; in rtl92se_get_hw_reg()
31 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92se_get_hw_reg()
35 *((bool *) (val)) = ppsc->fw_current_inpsmode; in rtl92se_get_hw_reg()
51 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; in rtl92se_get_hw_reg()
81 if (rtlhal->version == VERSION_8192S_ACUT) in rtl92se_set_hw_reg()
120 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
129 reg_tmp = (mac->cur_40_prime_sc) << 5; in rtl92se_set_hw_reg()
[all …]
H A Ddm.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
56 u32 edca_be_ul = edca_setting_ul[mac->vendor]; in _rtl92s_dm_check_edca_turbo()
57 u32 edca_be_dl = edca_setting_dl[mac->vendor]; in _rtl92s_dm_check_edca_turbo()
58 u32 edca_gmode = edca_setting_dl_gmode[mac->vendor]; in _rtl92s_dm_check_edca_turbo()
60 if (mac->link_state != MAC80211_LINKED) { in _rtl92s_dm_check_edca_turbo()
61 rtlpriv->dm.current_turbo_edca = false; in _rtl92s_dm_check_edca_turbo()
65 if ((!rtlpriv->dm.is_any_nonbepkts) && in _rtl92s_dm_check_edca_turbo()
66 (!rtlpriv->dm.disable_framebursting)) { in _rtl92s_dm_check_edca_turbo()
67 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; in _rtl92s_dm_check_edca_turbo()
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192du/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "../efuse.h"
84 /* channels 1-14. */
89 /* channels 36-64 */
95 /* channels 100-165 */
165 if (rtlhal->during_mac1init_radioa) in rtl92du_phy_query_bb_reg()
167 else if (rtlhal->during_mac0init_radiob) in rtl92du_phy_query_bb_reg()
190 if (rtlhal->during_mac1init_radioa) in rtl92du_phy_set_bb_reg()
192 else if (rtlhal->during_mac0init_radiob) in rtl92du_phy_set_bb_reg()
245 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { in rtl92du_phy_mac_config()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Dhw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
5 #include "../efuse.h"
29 rtlpci->reg_bcn_ctrl_val |= set_bits; in _rtl92ee_set_bcn_ctrl_reg()
30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; in _rtl92ee_set_bcn_ctrl_reg()
32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); in _rtl92ee_set_bcn_ctrl_reg()
80 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, in _rtl92ee_set_fw_clock_on()
83 if (!rtlhal->fw_ready) in _rtl92ee_set_fw_clock_on()
85 if (!rtlpriv->psc.fw_current_inpsmode) in _rtl92ee_set_fw_clock_on()
89 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192d/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
7 /* ----------------------------------------------------- */
9 /* ----------------------------------------------------- */
76 /* ----------------------------------------------------- */
78 /* ----------------------------------------------------- */
123 /* ----------------------------------------------------- */
125 /* ----------------------------------------------------- */
133 /* ----------------------------------------------------- */
135 /* ----------------------------------------------------- */
[all …]
/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_csr.h1 /* SPDX-License-Identifier: GPL-2.0 */
151 /* Mailbox PF->VF PF Accessible Data registers */
206 * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers
226 * struct aqm_grp_execmsk_lo - Available AE engines for the group
243 * struct aqm_grp_execmsk_hi - Available AE engines for the group
260 * struct aqmq_drbl - AQM Queue Doorbell Counter Registers
277 * struct aqmq_qsz - AQM Queue Host Queue Size Registers
295 * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers
313 * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers
337 * struct aqmq_en - AQM Queue Enable Registers
[all …]

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