Lines Matching +full:efuse +full:- +full:settings
1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8192e specific subdriver
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
467 struct device *dev = &priv->udev->dev; in rtl8192eu_identify_chip()
472 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8192eu_identify_chip()
475 ret = -ENOTSUPP; in rtl8192eu_identify_chip()
482 strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
483 priv->tx_paths = 1; in rtl8192eu_identify_chip()
484 priv->rtl_chip = RTL8191E; in rtl8192eu_identify_chip()
486 strscpy(priv->chip_name, "8192EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
487 priv->tx_paths = 2; in rtl8192eu_identify_chip()
488 priv->rtl_chip = RTL8192E; in rtl8192eu_identify_chip()
490 priv->rf_paths = 2; in rtl8192eu_identify_chip()
491 priv->rx_paths = 2; in rtl8192eu_identify_chip()
492 priv->has_wifi = 1; in rtl8192eu_identify_chip()
498 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192eu_identify_chip()
505 if (!priv->ep_tx_count) in rtl8192eu_identify_chip()
522 cck = priv->cck_tx_power_index_A[group]; in rtl8192e_set_tx_power()
534 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
535 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; in rtl8192e_set_tx_power()
541 mcsbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
543 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
545 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
553 if (priv->tx_paths > 1) { in rtl8192e_set_tx_power()
554 cck = priv->cck_tx_power_index_B[group]; in rtl8192e_set_tx_power()
566 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
567 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; in rtl8192e_set_tx_power()
574 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
576 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
578 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
590 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; in rtl8192eu_parse_efuse() local
593 if (efuse->rtl_id != cpu_to_le16(0x8129)) in rtl8192eu_parse_efuse()
594 return -EINVAL; in rtl8192eu_parse_efuse()
596 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8192eu_parse_efuse()
598 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8192eu_parse_efuse()
599 sizeof(efuse->tx_power_index_A.cck_base)); in rtl8192eu_parse_efuse()
600 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8192eu_parse_efuse()
601 sizeof(efuse->tx_power_index_B.cck_base)); in rtl8192eu_parse_efuse()
603 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8192eu_parse_efuse()
604 efuse->tx_power_index_A.ht40_base, in rtl8192eu_parse_efuse()
605 sizeof(efuse->tx_power_index_A.ht40_base)); in rtl8192eu_parse_efuse()
606 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8192eu_parse_efuse()
607 efuse->tx_power_index_B.ht40_base, in rtl8192eu_parse_efuse()
608 sizeof(efuse->tx_power_index_B.ht40_base)); in rtl8192eu_parse_efuse()
610 priv->ht20_tx_power_diff[0].a = in rtl8192eu_parse_efuse()
611 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; in rtl8192eu_parse_efuse()
612 priv->ht20_tx_power_diff[0].b = in rtl8192eu_parse_efuse()
613 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; in rtl8192eu_parse_efuse()
615 priv->ht40_tx_power_diff[0].a = 0; in rtl8192eu_parse_efuse()
616 priv->ht40_tx_power_diff[0].b = 0; in rtl8192eu_parse_efuse()
619 priv->ofdm_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
620 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; in rtl8192eu_parse_efuse()
621 priv->ofdm_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
622 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; in rtl8192eu_parse_efuse()
624 priv->ht20_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
625 efuse->tx_power_index_A.pwr_diff[i - 1].ht20; in rtl8192eu_parse_efuse()
626 priv->ht20_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
627 efuse->tx_power_index_B.pwr_diff[i - 1].ht20; in rtl8192eu_parse_efuse()
629 priv->ht40_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
630 efuse->tx_power_index_A.pwr_diff[i - 1].ht40; in rtl8192eu_parse_efuse()
631 priv->ht40_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
632 efuse->tx_power_index_B.pwr_diff[i - 1].ht40; in rtl8192eu_parse_efuse()
635 priv->default_crystal_cap = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; in rtl8192eu_parse_efuse()
673 if (priv->hi_pa) in rtl8192eu_init_phy_bb()
773 /* path-A IQK setting */ in rtl8192eu_rx_iqk_path_a()
863 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", in rtl8192eu_rx_iqk_path_a()
913 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", in rtl8192eu_iqk_path_b()
949 /* path-A IQK setting */ in rtl8192eu_rx_iqk_path_b()
1043 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", in rtl8192eu_rx_iqk_path_b()
1053 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iqcalibrate()
1087 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1089 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1091 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1096 /* MAC settings */ in rtl8192eu_phy_iqcalibrate()
1097 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1156 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1205 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1209 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1213 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1221 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1238 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iq_calibrate()
1247 candidate = -1; in rtl8192eu_phy_iq_calibrate()
1292 priv->rege94 = reg_e94; in rtl8192eu_phy_iq_calibrate()
1294 priv->rege9c = reg_e9c; in rtl8192eu_phy_iq_calibrate()
1298 priv->regeb4 = reg_eb4; in rtl8192eu_phy_iq_calibrate()
1300 priv->regebc = reg_ebc; in rtl8192eu_phy_iq_calibrate()
1311 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8192eu_phy_iq_calibrate()
1312 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8192eu_phy_iq_calibrate()
1319 if (priv->rf_paths > 1) in rtl8192eu_phy_iq_calibrate()
1324 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iq_calibrate()
1394 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { in rtl8192e_emu_to_active()
1403 ret = -EBUSY; in rtl8192e_emu_to_active()
1419 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { in rtl8192e_emu_to_active()
1429 ret = -EBUSY; in rtl8192e_emu_to_active()
1439 struct device *dev = &priv->udev->dev; in rtl8192eu_active_to_lps()
1448 retval = -EBUSY; in rtl8192eu_active_to_lps()
1458 } while (retry--); in rtl8192eu_active_to_lps()
1462 retval = -EBUSY; in rtl8192eu_active_to_lps()
1516 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { in rtl8192eu_active_to_emu()
1524 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", in rtl8192eu_active_to_emu()
1526 ret = -EBUSY; in rtl8192eu_active_to_emu()
1663 * Fix external switch Main->S1, Aux->S0 in rtl8192e_enable_rf()
1677 static const s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; in rtl8192e_cck_rssi()
1678 static const s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36}; in rtl8192e_cck_rssi()
1680 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; in rtl8192e_cck_rssi()
1688 if (priv->cck_agc_report_type == 0) in rtl8192e_cck_rssi()
1693 rx_pwr_all = lna_gain - (2 * vga_idx); in rtl8192e_cck_rssi()