1028fa281SKalle Valo // SPDX-License-Identifier: GPL-2.0-only
2028fa281SKalle Valo /*
3028fa281SKalle Valo * RTL8XXXU mac80211 USB driver - 8723b specific subdriver
4028fa281SKalle Valo *
5028fa281SKalle Valo * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6028fa281SKalle Valo *
7028fa281SKalle Valo * Portions, notably calibration code:
8028fa281SKalle Valo * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9028fa281SKalle Valo *
10028fa281SKalle Valo * This driver was written as a replacement for the vendor provided
11028fa281SKalle Valo * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12028fa281SKalle Valo * their programming interface, I have started adding support for
13028fa281SKalle Valo * additional 8xxx chips like the 8192cu, 8188cus, etc.
14028fa281SKalle Valo */
15028fa281SKalle Valo
16028fa281SKalle Valo #include "regs.h"
17*949f6f3aSPing-Ke Shih #include "rtl8xxxu.h"
18028fa281SKalle Valo
19028fa281SKalle Valo static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
20028fa281SKalle Valo {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
21028fa281SKalle Valo {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
22028fa281SKalle Valo {0x430, 0x00}, {0x431, 0x00},
23028fa281SKalle Valo {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
24028fa281SKalle Valo {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
25028fa281SKalle Valo {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
26028fa281SKalle Valo {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
27028fa281SKalle Valo {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
28028fa281SKalle Valo {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
29028fa281SKalle Valo {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
30028fa281SKalle Valo {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
31028fa281SKalle Valo {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
32028fa281SKalle Valo {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
33028fa281SKalle Valo {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
34028fa281SKalle Valo {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
35028fa281SKalle Valo {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
36028fa281SKalle Valo {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
37028fa281SKalle Valo {0x516, 0x0a}, {0x525, 0x4f},
38028fa281SKalle Valo {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
39028fa281SKalle Valo {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
40028fa281SKalle Valo {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
41028fa281SKalle Valo {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
42028fa281SKalle Valo {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
43028fa281SKalle Valo {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
44028fa281SKalle Valo {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
45028fa281SKalle Valo {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
46028fa281SKalle Valo {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
47028fa281SKalle Valo {0xffff, 0xff},
48028fa281SKalle Valo };
49028fa281SKalle Valo
50028fa281SKalle Valo static const struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
51028fa281SKalle Valo {0x800, 0x80040000}, {0x804, 0x00000003},
52028fa281SKalle Valo {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
53028fa281SKalle Valo {0x810, 0x10001331}, {0x814, 0x020c3d10},
54028fa281SKalle Valo {0x818, 0x02200385}, {0x81c, 0x00000000},
55028fa281SKalle Valo {0x820, 0x01000100}, {0x824, 0x00190204},
56028fa281SKalle Valo {0x828, 0x00000000}, {0x82c, 0x00000000},
57028fa281SKalle Valo {0x830, 0x00000000}, {0x834, 0x00000000},
58028fa281SKalle Valo {0x838, 0x00000000}, {0x83c, 0x00000000},
59028fa281SKalle Valo {0x840, 0x00010000}, {0x844, 0x00000000},
60028fa281SKalle Valo {0x848, 0x00000000}, {0x84c, 0x00000000},
61028fa281SKalle Valo {0x850, 0x00000000}, {0x854, 0x00000000},
62028fa281SKalle Valo {0x858, 0x569a11a9}, {0x85c, 0x01000014},
63028fa281SKalle Valo {0x860, 0x66f60110}, {0x864, 0x061f0649},
64028fa281SKalle Valo {0x868, 0x00000000}, {0x86c, 0x27272700},
65028fa281SKalle Valo {0x870, 0x07000760}, {0x874, 0x25004000},
66028fa281SKalle Valo {0x878, 0x00000808}, {0x87c, 0x00000000},
67028fa281SKalle Valo {0x880, 0xb0000c1c}, {0x884, 0x00000001},
68028fa281SKalle Valo {0x888, 0x00000000}, {0x88c, 0xccc000c0},
69028fa281SKalle Valo {0x890, 0x00000800}, {0x894, 0xfffffffe},
70028fa281SKalle Valo {0x898, 0x40302010}, {0x89c, 0x00706050},
71028fa281SKalle Valo {0x900, 0x00000000}, {0x904, 0x00000023},
72028fa281SKalle Valo {0x908, 0x00000000}, {0x90c, 0x81121111},
73028fa281SKalle Valo {0x910, 0x00000002}, {0x914, 0x00000201},
74028fa281SKalle Valo {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
75028fa281SKalle Valo {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
76028fa281SKalle Valo {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
77028fa281SKalle Valo {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
78028fa281SKalle Valo {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
79028fa281SKalle Valo {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
80028fa281SKalle Valo {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
81028fa281SKalle Valo {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
82028fa281SKalle Valo {0xa80, 0x21806490}, {0xb2c, 0x00000000},
83028fa281SKalle Valo {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
84028fa281SKalle Valo {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
85028fa281SKalle Valo {0xc10, 0x08800000}, {0xc14, 0x40000100},
86028fa281SKalle Valo {0xc18, 0x08800000}, {0xc1c, 0x40000100},
87028fa281SKalle Valo {0xc20, 0x00000000}, {0xc24, 0x00000000},
88028fa281SKalle Valo {0xc28, 0x00000000}, {0xc2c, 0x00000000},
89028fa281SKalle Valo {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
90028fa281SKalle Valo {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
91028fa281SKalle Valo {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
92028fa281SKalle Valo {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
93028fa281SKalle Valo {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
94028fa281SKalle Valo {0xc58, 0x00013149}, {0xc5c, 0x00250492},
95028fa281SKalle Valo {0xc60, 0x00000000}, {0xc64, 0x7112848b},
96028fa281SKalle Valo {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
97028fa281SKalle Valo {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
98028fa281SKalle Valo {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
99028fa281SKalle Valo {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
100028fa281SKalle Valo {0xc88, 0x40000100}, {0xc8c, 0x20200000},
101028fa281SKalle Valo {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
102028fa281SKalle Valo {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
103028fa281SKalle Valo {0xca0, 0x00000000}, {0xca4, 0x000300a0},
104028fa281SKalle Valo {0xca8, 0x00000000}, {0xcac, 0x00000000},
105028fa281SKalle Valo {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
106028fa281SKalle Valo {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
107028fa281SKalle Valo {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
108028fa281SKalle Valo {0xcc8, 0x00000000}, {0xccc, 0x00000000},
109028fa281SKalle Valo {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
110028fa281SKalle Valo {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
111028fa281SKalle Valo {0xce0, 0x00222222}, {0xce4, 0x00000000},
112028fa281SKalle Valo {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
113028fa281SKalle Valo {0xd00, 0x00000740}, {0xd04, 0x40020401},
114028fa281SKalle Valo {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
115028fa281SKalle Valo {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
116028fa281SKalle Valo {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
117028fa281SKalle Valo {0xd30, 0x00000000}, {0xd34, 0x80608000},
118028fa281SKalle Valo {0xd38, 0x00000000}, {0xd3c, 0x00127353},
119028fa281SKalle Valo {0xd40, 0x00000000}, {0xd44, 0x00000000},
120028fa281SKalle Valo {0xd48, 0x00000000}, {0xd4c, 0x00000000},
121028fa281SKalle Valo {0xd50, 0x6437140a}, {0xd54, 0x00000000},
122028fa281SKalle Valo {0xd58, 0x00000282}, {0xd5c, 0x30032064},
123028fa281SKalle Valo {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
124028fa281SKalle Valo {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
125028fa281SKalle Valo {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
126028fa281SKalle Valo {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
127028fa281SKalle Valo {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
128028fa281SKalle Valo {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
129028fa281SKalle Valo {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
130028fa281SKalle Valo {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
131028fa281SKalle Valo {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
132028fa281SKalle Valo {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
133028fa281SKalle Valo {0xe44, 0x01004800}, {0xe48, 0xfb000000},
134028fa281SKalle Valo {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
135028fa281SKalle Valo {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
136028fa281SKalle Valo {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
137028fa281SKalle Valo {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
138028fa281SKalle Valo {0xe70, 0x00c00096}, {0xe74, 0x01000056},
139028fa281SKalle Valo {0xe78, 0x01000014}, {0xe7c, 0x01000056},
140028fa281SKalle Valo {0xe80, 0x01000014}, {0xe84, 0x00c00096},
141028fa281SKalle Valo {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
142028fa281SKalle Valo {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
143028fa281SKalle Valo {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
144028fa281SKalle Valo {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
145028fa281SKalle Valo {0xf14, 0x00000003}, {0xf4c, 0x00000000},
146028fa281SKalle Valo {0xf00, 0x00000300},
147028fa281SKalle Valo {0x820, 0x01000100}, {0x800, 0x83040000},
148028fa281SKalle Valo {0xffff, 0xffffffff},
149028fa281SKalle Valo };
150028fa281SKalle Valo
151028fa281SKalle Valo static const struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
152028fa281SKalle Valo {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
153028fa281SKalle Valo {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
154028fa281SKalle Valo {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
155028fa281SKalle Valo {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
156028fa281SKalle Valo {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
157028fa281SKalle Valo {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
158028fa281SKalle Valo {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
159028fa281SKalle Valo {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
160028fa281SKalle Valo {0xc78, 0xed100001}, {0xc78, 0xec110001},
161028fa281SKalle Valo {0xc78, 0xeb120001}, {0xc78, 0xea130001},
162028fa281SKalle Valo {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
163028fa281SKalle Valo {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
164028fa281SKalle Valo {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
165028fa281SKalle Valo {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
166028fa281SKalle Valo {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
167028fa281SKalle Valo {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
168028fa281SKalle Valo {0xc78, 0x65200001}, {0xc78, 0x64210001},
169028fa281SKalle Valo {0xc78, 0x63220001}, {0xc78, 0x4a230001},
170028fa281SKalle Valo {0xc78, 0x49240001}, {0xc78, 0x48250001},
171028fa281SKalle Valo {0xc78, 0x47260001}, {0xc78, 0x46270001},
172028fa281SKalle Valo {0xc78, 0x45280001}, {0xc78, 0x44290001},
173028fa281SKalle Valo {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
174028fa281SKalle Valo {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
175028fa281SKalle Valo {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
176028fa281SKalle Valo {0xc78, 0x0a300001}, {0xc78, 0x09310001},
177028fa281SKalle Valo {0xc78, 0x08320001}, {0xc78, 0x07330001},
178028fa281SKalle Valo {0xc78, 0x06340001}, {0xc78, 0x05350001},
179028fa281SKalle Valo {0xc78, 0x04360001}, {0xc78, 0x03370001},
180028fa281SKalle Valo {0xc78, 0x02380001}, {0xc78, 0x01390001},
181028fa281SKalle Valo {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
182028fa281SKalle Valo {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
183028fa281SKalle Valo {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
184028fa281SKalle Valo {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
185028fa281SKalle Valo {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
186028fa281SKalle Valo {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
187028fa281SKalle Valo {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
188028fa281SKalle Valo {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
189028fa281SKalle Valo {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
190028fa281SKalle Valo {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
191028fa281SKalle Valo {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
192028fa281SKalle Valo {0xc78, 0xec500001}, {0xc78, 0xeb510001},
193028fa281SKalle Valo {0xc78, 0xea520001}, {0xc78, 0xe9530001},
194028fa281SKalle Valo {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
195028fa281SKalle Valo {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
196028fa281SKalle Valo {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
197028fa281SKalle Valo {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
198028fa281SKalle Valo {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
199028fa281SKalle Valo {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
200028fa281SKalle Valo {0xc78, 0x65600001}, {0xc78, 0x64610001},
201028fa281SKalle Valo {0xc78, 0x63620001}, {0xc78, 0x62630001},
202028fa281SKalle Valo {0xc78, 0x61640001}, {0xc78, 0x48650001},
203028fa281SKalle Valo {0xc78, 0x47660001}, {0xc78, 0x46670001},
204028fa281SKalle Valo {0xc78, 0x45680001}, {0xc78, 0x44690001},
205028fa281SKalle Valo {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
206028fa281SKalle Valo {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
207028fa281SKalle Valo {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
208028fa281SKalle Valo {0xc78, 0x24700001}, {0xc78, 0x09710001},
209028fa281SKalle Valo {0xc78, 0x08720001}, {0xc78, 0x07730001},
210028fa281SKalle Valo {0xc78, 0x06740001}, {0xc78, 0x05750001},
211028fa281SKalle Valo {0xc78, 0x04760001}, {0xc78, 0x03770001},
212028fa281SKalle Valo {0xc78, 0x02780001}, {0xc78, 0x01790001},
213028fa281SKalle Valo {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
214028fa281SKalle Valo {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
215028fa281SKalle Valo {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
216028fa281SKalle Valo {0xc50, 0x69553422},
217028fa281SKalle Valo {0xc50, 0x69553420},
218028fa281SKalle Valo {0x824, 0x00390204},
219028fa281SKalle Valo {0xffff, 0xffffffff}
220028fa281SKalle Valo };
221028fa281SKalle Valo
222028fa281SKalle Valo static const struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
223028fa281SKalle Valo {0x00, 0x00010000}, {0xb0, 0x000dffe0},
224028fa281SKalle Valo {0xfe, 0x00000000}, {0xfe, 0x00000000},
225028fa281SKalle Valo {0xfe, 0x00000000}, {0xb1, 0x00000018},
226028fa281SKalle Valo {0xfe, 0x00000000}, {0xfe, 0x00000000},
227028fa281SKalle Valo {0xfe, 0x00000000}, {0xb2, 0x00084c00},
228028fa281SKalle Valo {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
229028fa281SKalle Valo {0xb7, 0x00000010}, {0xb8, 0x0000907f},
230028fa281SKalle Valo {0x5c, 0x00000002}, {0x7c, 0x00000002},
231028fa281SKalle Valo {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
232028fa281SKalle Valo {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
233028fa281SKalle Valo {0x1e, 0x00000000}, {0xdf, 0x00000780},
234028fa281SKalle Valo {0x50, 0x00067435},
235028fa281SKalle Valo /*
236028fa281SKalle Valo * The 8723bu vendor driver indicates that bit 8 should be set in
237028fa281SKalle Valo * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
238028fa281SKalle Valo * they never actually check the package type - and just default
239028fa281SKalle Valo * to not setting it.
240028fa281SKalle Valo */
241028fa281SKalle Valo {0x51, 0x0006b04e},
242028fa281SKalle Valo {0x52, 0x000007d2}, {0x53, 0x00000000},
243028fa281SKalle Valo {0x54, 0x00050400}, {0x55, 0x0004026e},
244028fa281SKalle Valo {0xdd, 0x0000004c}, {0x70, 0x00067435},
245028fa281SKalle Valo /*
246028fa281SKalle Valo * 0x71 has same package type condition as for register 0x51
247028fa281SKalle Valo */
248028fa281SKalle Valo {0x71, 0x0006b04e},
249028fa281SKalle Valo {0x72, 0x000007d2}, {0x73, 0x00000000},
250028fa281SKalle Valo {0x74, 0x00050400}, {0x75, 0x0004026e},
251028fa281SKalle Valo {0xef, 0x00000100}, {0x34, 0x0000add7},
252028fa281SKalle Valo {0x35, 0x00005c00}, {0x34, 0x00009dd4},
253028fa281SKalle Valo {0x35, 0x00005000}, {0x34, 0x00008dd1},
254028fa281SKalle Valo {0x35, 0x00004400}, {0x34, 0x00007dce},
255028fa281SKalle Valo {0x35, 0x00003800}, {0x34, 0x00006cd1},
256028fa281SKalle Valo {0x35, 0x00004400}, {0x34, 0x00005cce},
257028fa281SKalle Valo {0x35, 0x00003800}, {0x34, 0x000048ce},
258028fa281SKalle Valo {0x35, 0x00004400}, {0x34, 0x000034ce},
259028fa281SKalle Valo {0x35, 0x00003800}, {0x34, 0x00002451},
260028fa281SKalle Valo {0x35, 0x00004400}, {0x34, 0x0000144e},
261028fa281SKalle Valo {0x35, 0x00003800}, {0x34, 0x00000051},
262028fa281SKalle Valo {0x35, 0x00004400}, {0xef, 0x00000000},
263028fa281SKalle Valo {0xef, 0x00000100}, {0xed, 0x00000010},
264028fa281SKalle Valo {0x44, 0x0000add7}, {0x44, 0x00009dd4},
265028fa281SKalle Valo {0x44, 0x00008dd1}, {0x44, 0x00007dce},
266028fa281SKalle Valo {0x44, 0x00006cc1}, {0x44, 0x00005cce},
267028fa281SKalle Valo {0x44, 0x000044d1}, {0x44, 0x000034ce},
268028fa281SKalle Valo {0x44, 0x00002451}, {0x44, 0x0000144e},
269028fa281SKalle Valo {0x44, 0x00000051}, {0xef, 0x00000000},
270028fa281SKalle Valo {0xed, 0x00000000}, {0x7f, 0x00020080},
271028fa281SKalle Valo {0xef, 0x00002000}, {0x3b, 0x000380ef},
272028fa281SKalle Valo {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
273028fa281SKalle Valo {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
274028fa281SKalle Valo {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
275028fa281SKalle Valo {0x3b, 0x00000900}, {0xef, 0x00000000},
276028fa281SKalle Valo {0xed, 0x00000001}, {0x40, 0x000380ef},
277028fa281SKalle Valo {0x40, 0x000302fe}, {0x40, 0x00028ce6},
278028fa281SKalle Valo {0x40, 0x000200bc}, {0x40, 0x000188a5},
279028fa281SKalle Valo {0x40, 0x00010fbc}, {0x40, 0x00008f71},
280028fa281SKalle Valo {0x40, 0x00000900}, {0xed, 0x00000000},
281028fa281SKalle Valo {0x82, 0x00080000}, {0x83, 0x00008000},
282028fa281SKalle Valo {0x84, 0x00048d80}, {0x85, 0x00068000},
283028fa281SKalle Valo {0xa2, 0x00080000}, {0xa3, 0x00008000},
284028fa281SKalle Valo {0xa4, 0x00048d80}, {0xa5, 0x00068000},
285028fa281SKalle Valo {0xed, 0x00000002}, {0xef, 0x00000002},
286028fa281SKalle Valo {0x56, 0x00000032}, {0x76, 0x00000032},
287028fa281SKalle Valo {0x01, 0x00000780},
288028fa281SKalle Valo {0xff, 0xffffffff}
289028fa281SKalle Valo };
290028fa281SKalle Valo
rtl8723bu_identify_chip(struct rtl8xxxu_priv * priv)291028fa281SKalle Valo static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv)
292028fa281SKalle Valo {
293028fa281SKalle Valo struct device *dev = &priv->udev->dev;
294028fa281SKalle Valo u32 val32, sys_cfg, vendor;
295028fa281SKalle Valo int ret = 0;
296028fa281SKalle Valo
297028fa281SKalle Valo sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
298028fa281SKalle Valo priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
299028fa281SKalle Valo if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
300028fa281SKalle Valo dev_info(dev, "Unsupported test chip\n");
301028fa281SKalle Valo ret = -ENOTSUPP;
302028fa281SKalle Valo goto out;
303028fa281SKalle Valo }
304028fa281SKalle Valo
305028fa281SKalle Valo strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name));
306028fa281SKalle Valo priv->rtl_chip = RTL8723B;
307028fa281SKalle Valo priv->rf_paths = 1;
308028fa281SKalle Valo priv->rx_paths = 1;
309028fa281SKalle Valo priv->tx_paths = 1;
310028fa281SKalle Valo
311028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
312028fa281SKalle Valo if (val32 & MULTI_WIFI_FUNC_EN)
313028fa281SKalle Valo priv->has_wifi = 1;
314028fa281SKalle Valo if (val32 & MULTI_BT_FUNC_EN)
315028fa281SKalle Valo priv->has_bluetooth = 1;
316028fa281SKalle Valo if (val32 & MULTI_GPS_FUNC_EN)
317028fa281SKalle Valo priv->has_gps = 1;
318028fa281SKalle Valo priv->is_multi_func = 1;
319028fa281SKalle Valo
320028fa281SKalle Valo vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK;
321028fa281SKalle Valo rtl8xxxu_identify_vendor_2bits(priv, vendor);
322028fa281SKalle Valo
323028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
324028fa281SKalle Valo priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);
325028fa281SKalle Valo
326028fa281SKalle Valo rtl8xxxu_config_endpoints_sie(priv);
327028fa281SKalle Valo
328028fa281SKalle Valo /*
329028fa281SKalle Valo * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
330028fa281SKalle Valo */
331028fa281SKalle Valo if (!priv->ep_tx_count)
332028fa281SKalle Valo ret = rtl8xxxu_config_endpoints_no_sie(priv);
333028fa281SKalle Valo
334028fa281SKalle Valo out:
335028fa281SKalle Valo return ret;
336028fa281SKalle Valo }
337028fa281SKalle Valo
rtl8723bu_write_btreg(struct rtl8xxxu_priv * priv,u8 reg,u8 data)338028fa281SKalle Valo static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
339028fa281SKalle Valo {
340028fa281SKalle Valo struct h2c_cmd h2c;
341028fa281SKalle Valo int reqnum = 0;
342028fa281SKalle Valo
343028fa281SKalle Valo memset(&h2c, 0, sizeof(struct h2c_cmd));
344028fa281SKalle Valo h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
345028fa281SKalle Valo h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
346028fa281SKalle Valo h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
347028fa281SKalle Valo h2c.bt_mp_oper.data = data;
348028fa281SKalle Valo rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
349028fa281SKalle Valo
350028fa281SKalle Valo reqnum++;
351028fa281SKalle Valo memset(&h2c, 0, sizeof(struct h2c_cmd));
352028fa281SKalle Valo h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
353028fa281SKalle Valo h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
354028fa281SKalle Valo h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
355028fa281SKalle Valo h2c.bt_mp_oper.addr = reg;
356028fa281SKalle Valo rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
357028fa281SKalle Valo }
358028fa281SKalle Valo
rtl8723bu_reset_8051(struct rtl8xxxu_priv * priv)359028fa281SKalle Valo static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
360028fa281SKalle Valo {
361028fa281SKalle Valo u8 val8;
362028fa281SKalle Valo u16 sys_func;
363028fa281SKalle Valo
364028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
365028fa281SKalle Valo val8 &= ~BIT(1);
366028fa281SKalle Valo rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
367028fa281SKalle Valo
368028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
369028fa281SKalle Valo val8 &= ~BIT(0);
370028fa281SKalle Valo rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
371028fa281SKalle Valo
372028fa281SKalle Valo sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
373028fa281SKalle Valo sys_func &= ~SYS_FUNC_CPU_ENABLE;
374028fa281SKalle Valo rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
375028fa281SKalle Valo
376028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
377028fa281SKalle Valo val8 &= ~BIT(1);
378028fa281SKalle Valo rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
379028fa281SKalle Valo
380028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
381028fa281SKalle Valo val8 |= BIT(0);
382028fa281SKalle Valo rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
383028fa281SKalle Valo
384028fa281SKalle Valo sys_func |= SYS_FUNC_CPU_ENABLE;
385028fa281SKalle Valo rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
386028fa281SKalle Valo }
387028fa281SKalle Valo
388028fa281SKalle Valo static void
rtl8723b_set_tx_power(struct rtl8xxxu_priv * priv,int channel,bool ht40)389028fa281SKalle Valo rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
390028fa281SKalle Valo {
391028fa281SKalle Valo u32 val32, ofdm, mcs;
392028fa281SKalle Valo u8 cck, ofdmbase, mcsbase;
393028fa281SKalle Valo int group, tx_idx;
394028fa281SKalle Valo
395028fa281SKalle Valo tx_idx = 0;
396028fa281SKalle Valo group = rtl8xxxu_gen2_channel_to_group(channel);
397028fa281SKalle Valo
398028fa281SKalle Valo cck = priv->cck_tx_power_index_B[group];
399028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
400028fa281SKalle Valo val32 &= 0xffff00ff;
401028fa281SKalle Valo val32 |= (cck << 8);
402028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
403028fa281SKalle Valo
404028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
405028fa281SKalle Valo val32 &= 0xff;
406028fa281SKalle Valo val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
407028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
408028fa281SKalle Valo
409028fa281SKalle Valo ofdmbase = priv->ht40_1s_tx_power_index_B[group];
410028fa281SKalle Valo ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
411028fa281SKalle Valo ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
412028fa281SKalle Valo
413028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
414028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
415028fa281SKalle Valo
416028fa281SKalle Valo mcsbase = priv->ht40_1s_tx_power_index_B[group];
417028fa281SKalle Valo if (ht40)
418028fa281SKalle Valo mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
419028fa281SKalle Valo else
420028fa281SKalle Valo mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
421028fa281SKalle Valo mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
422028fa281SKalle Valo
423028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
424028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
425028fa281SKalle Valo }
426028fa281SKalle Valo
rtl8723bu_parse_efuse(struct rtl8xxxu_priv * priv)427028fa281SKalle Valo static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
428028fa281SKalle Valo {
429028fa281SKalle Valo struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
430028fa281SKalle Valo int i;
431028fa281SKalle Valo
432028fa281SKalle Valo if (efuse->rtl_id != cpu_to_le16(0x8129))
433028fa281SKalle Valo return -EINVAL;
434028fa281SKalle Valo
435028fa281SKalle Valo ether_addr_copy(priv->mac_addr, efuse->mac_addr);
436028fa281SKalle Valo
437028fa281SKalle Valo memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
438028fa281SKalle Valo sizeof(efuse->tx_power_index_A.cck_base));
439028fa281SKalle Valo memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
440028fa281SKalle Valo sizeof(efuse->tx_power_index_B.cck_base));
441028fa281SKalle Valo
442028fa281SKalle Valo memcpy(priv->ht40_1s_tx_power_index_A,
443028fa281SKalle Valo efuse->tx_power_index_A.ht40_base,
444028fa281SKalle Valo sizeof(efuse->tx_power_index_A.ht40_base));
445028fa281SKalle Valo memcpy(priv->ht40_1s_tx_power_index_B,
446028fa281SKalle Valo efuse->tx_power_index_B.ht40_base,
447028fa281SKalle Valo sizeof(efuse->tx_power_index_B.ht40_base));
448028fa281SKalle Valo
449028fa281SKalle Valo priv->ofdm_tx_power_diff[0].a =
450028fa281SKalle Valo efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
451028fa281SKalle Valo priv->ofdm_tx_power_diff[0].b =
452028fa281SKalle Valo efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
453028fa281SKalle Valo
454028fa281SKalle Valo priv->ht20_tx_power_diff[0].a =
455028fa281SKalle Valo efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
456028fa281SKalle Valo priv->ht20_tx_power_diff[0].b =
457028fa281SKalle Valo efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
458028fa281SKalle Valo
459028fa281SKalle Valo priv->ht40_tx_power_diff[0].a = 0;
460028fa281SKalle Valo priv->ht40_tx_power_diff[0].b = 0;
461028fa281SKalle Valo
462028fa281SKalle Valo for (i = 1; i < RTL8723B_TX_COUNT; i++) {
463028fa281SKalle Valo priv->ofdm_tx_power_diff[i].a =
464028fa281SKalle Valo efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
465028fa281SKalle Valo priv->ofdm_tx_power_diff[i].b =
466028fa281SKalle Valo efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
467028fa281SKalle Valo
468028fa281SKalle Valo priv->ht20_tx_power_diff[i].a =
469028fa281SKalle Valo efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
470028fa281SKalle Valo priv->ht20_tx_power_diff[i].b =
471028fa281SKalle Valo efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
472028fa281SKalle Valo
473028fa281SKalle Valo priv->ht40_tx_power_diff[i].a =
474028fa281SKalle Valo efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
475028fa281SKalle Valo priv->ht40_tx_power_diff[i].b =
476028fa281SKalle Valo efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
477028fa281SKalle Valo }
478028fa281SKalle Valo
479028fa281SKalle Valo priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
480028fa281SKalle Valo
481028fa281SKalle Valo return 0;
482028fa281SKalle Valo }
483028fa281SKalle Valo
rtl8723bu_load_firmware(struct rtl8xxxu_priv * priv)484028fa281SKalle Valo static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
485028fa281SKalle Valo {
486028fa281SKalle Valo const char *fw_name;
487028fa281SKalle Valo int ret;
488028fa281SKalle Valo
489028fa281SKalle Valo if (priv->enable_bluetooth)
490028fa281SKalle Valo fw_name = "rtlwifi/rtl8723bu_bt.bin";
491028fa281SKalle Valo else
492028fa281SKalle Valo fw_name = "rtlwifi/rtl8723bu_nic.bin";
493028fa281SKalle Valo
494028fa281SKalle Valo ret = rtl8xxxu_load_firmware(priv, fw_name);
495028fa281SKalle Valo return ret;
496028fa281SKalle Valo }
497028fa281SKalle Valo
rtl8723bu_init_phy_bb(struct rtl8xxxu_priv * priv)498028fa281SKalle Valo static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv)
499028fa281SKalle Valo {
500028fa281SKalle Valo u8 val8;
501028fa281SKalle Valo u16 val16;
502028fa281SKalle Valo
503028fa281SKalle Valo val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
504028fa281SKalle Valo val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
505028fa281SKalle Valo rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
506028fa281SKalle Valo
507028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
508028fa281SKalle Valo
509028fa281SKalle Valo /* 6. 0x1f[7:0] = 0x07 */
510028fa281SKalle Valo val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
511028fa281SKalle Valo rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
512028fa281SKalle Valo
513028fa281SKalle Valo /* Why? */
514028fa281SKalle Valo rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
515028fa281SKalle Valo rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
516028fa281SKalle Valo rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
517028fa281SKalle Valo
518028fa281SKalle Valo rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
519028fa281SKalle Valo }
520028fa281SKalle Valo
rtl8723bu_init_phy_rf(struct rtl8xxxu_priv * priv)521028fa281SKalle Valo static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
522028fa281SKalle Valo {
523028fa281SKalle Valo int ret;
524028fa281SKalle Valo
525028fa281SKalle Valo ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A);
526028fa281SKalle Valo /*
527028fa281SKalle Valo * PHY LCK
528028fa281SKalle Valo */
529028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
530028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
531028fa281SKalle Valo msleep(200);
532028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
533028fa281SKalle Valo
534028fa281SKalle Valo return ret;
535028fa281SKalle Valo }
536028fa281SKalle Valo
rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv * priv)537028fa281SKalle Valo void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
538028fa281SKalle Valo {
539028fa281SKalle Valo u32 val32;
540028fa281SKalle Valo
541028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1);
542028fa281SKalle Valo val32 &= ~(BIT(20) | BIT(24));
543028fa281SKalle Valo rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32);
544028fa281SKalle Valo
545028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
546028fa281SKalle Valo val32 &= ~BIT(4);
547028fa281SKalle Valo rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
548028fa281SKalle Valo
549028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
550028fa281SKalle Valo val32 |= BIT(3);
551028fa281SKalle Valo rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
552028fa281SKalle Valo
553028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
554028fa281SKalle Valo val32 |= BIT(24);
555028fa281SKalle Valo rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
556028fa281SKalle Valo
557028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
558028fa281SKalle Valo val32 &= ~BIT(23);
559028fa281SKalle Valo rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
560028fa281SKalle Valo
561028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
562028fa281SKalle Valo val32 |= (BIT(0) | BIT(1));
563028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
564028fa281SKalle Valo
565028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
566028fa281SKalle Valo val32 &= 0xffffff00;
567028fa281SKalle Valo val32 |= 0x77;
568028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
569028fa281SKalle Valo
570028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
571028fa281SKalle Valo val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
572028fa281SKalle Valo rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
573028fa281SKalle Valo }
574028fa281SKalle Valo
rtl8723bu_iqk_path_a(struct rtl8xxxu_priv * priv)575028fa281SKalle Valo static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
576028fa281SKalle Valo {
577028fa281SKalle Valo u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
578028fa281SKalle Valo int result = 0;
579028fa281SKalle Valo
580028fa281SKalle Valo path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
581028fa281SKalle Valo
582028fa281SKalle Valo /*
583028fa281SKalle Valo * Leave IQK mode
584028fa281SKalle Valo */
585028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
586028fa281SKalle Valo val32 &= 0x000000ff;
587028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
588028fa281SKalle Valo
589028fa281SKalle Valo /*
590028fa281SKalle Valo * Enable path A PA in TX IQK mode
591028fa281SKalle Valo */
592028fa281SKalle Valo val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
593028fa281SKalle Valo val32 |= 0x80000;
594028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
595028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
596028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
597028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
598028fa281SKalle Valo
599028fa281SKalle Valo /*
600028fa281SKalle Valo * Tx IQK setting
601028fa281SKalle Valo */
602028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
603028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
604028fa281SKalle Valo
605028fa281SKalle Valo /* path-A IQK setting */
606028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
607028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
608028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
609028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
610028fa281SKalle Valo
611028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
612028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
613028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
614028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
615028fa281SKalle Valo
616028fa281SKalle Valo /* LO calibration setting */
617028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
618028fa281SKalle Valo
619028fa281SKalle Valo /*
620028fa281SKalle Valo * Enter IQK mode
621028fa281SKalle Valo */
622028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
623028fa281SKalle Valo val32 &= 0x000000ff;
624028fa281SKalle Valo val32 |= 0x80800000;
625028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
626028fa281SKalle Valo
627028fa281SKalle Valo /*
628028fa281SKalle Valo * The vendor driver indicates the USB module is always using
629028fa281SKalle Valo * S0S1 path 1 for the 8723bu. This may be different for 8192eu
630028fa281SKalle Valo */
631028fa281SKalle Valo if (priv->rf_paths > 1)
632028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
633028fa281SKalle Valo else
634028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
635028fa281SKalle Valo
636028fa281SKalle Valo /*
637028fa281SKalle Valo * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
638028fa281SKalle Valo * No trace of this in the 8192eu or 8188eu vendor drivers.
639028fa281SKalle Valo */
640028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
641028fa281SKalle Valo
642028fa281SKalle Valo /* One shot, path A LOK & IQK */
643028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
644028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
645028fa281SKalle Valo
646028fa281SKalle Valo mdelay(1);
647028fa281SKalle Valo
648028fa281SKalle Valo /* Restore Ant Path */
649028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
650028fa281SKalle Valo #ifdef RTL8723BU_BT
651028fa281SKalle Valo /* GNT_BT = 1 */
652028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
653028fa281SKalle Valo #endif
654028fa281SKalle Valo
655028fa281SKalle Valo /*
656028fa281SKalle Valo * Leave IQK mode
657028fa281SKalle Valo */
658028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
659028fa281SKalle Valo val32 &= 0x000000ff;
660028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
661028fa281SKalle Valo
662028fa281SKalle Valo /* Check failed */
663028fa281SKalle Valo reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
664028fa281SKalle Valo reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
665028fa281SKalle Valo reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
666028fa281SKalle Valo
667028fa281SKalle Valo val32 = (reg_e9c >> 16) & 0x3ff;
668028fa281SKalle Valo if (val32 & 0x200)
669028fa281SKalle Valo val32 = 0x400 - val32;
670028fa281SKalle Valo
671028fa281SKalle Valo if (!(reg_eac & BIT(28)) &&
672028fa281SKalle Valo ((reg_e94 & 0x03ff0000) != 0x01420000) &&
673028fa281SKalle Valo ((reg_e9c & 0x03ff0000) != 0x00420000) &&
674028fa281SKalle Valo ((reg_e94 & 0x03ff0000) < 0x01100000) &&
675028fa281SKalle Valo ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
676028fa281SKalle Valo val32 < 0xf)
677028fa281SKalle Valo result |= 0x01;
678028fa281SKalle Valo else /* If TX not OK, ignore RX */
679028fa281SKalle Valo goto out;
680028fa281SKalle Valo
681028fa281SKalle Valo out:
682028fa281SKalle Valo return result;
683028fa281SKalle Valo }
684028fa281SKalle Valo
rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv * priv)685028fa281SKalle Valo static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
686028fa281SKalle Valo {
687028fa281SKalle Valo u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
688028fa281SKalle Valo int result = 0;
689028fa281SKalle Valo
690028fa281SKalle Valo path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
691028fa281SKalle Valo
692028fa281SKalle Valo /*
693028fa281SKalle Valo * Leave IQK mode
694028fa281SKalle Valo */
695028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
696028fa281SKalle Valo val32 &= 0x000000ff;
697028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
698028fa281SKalle Valo
699028fa281SKalle Valo /*
700028fa281SKalle Valo * Enable path A PA in TX IQK mode
701028fa281SKalle Valo */
702028fa281SKalle Valo val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
703028fa281SKalle Valo val32 |= 0x80000;
704028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
705028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
706028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
707028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
708028fa281SKalle Valo
709028fa281SKalle Valo /*
710028fa281SKalle Valo * Tx IQK setting
711028fa281SKalle Valo */
712028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
713028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
714028fa281SKalle Valo
715028fa281SKalle Valo /* path-A IQK setting */
716028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
717028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
718028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
719028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
720028fa281SKalle Valo
721028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
722028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
723028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
724028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
725028fa281SKalle Valo
726028fa281SKalle Valo /* LO calibration setting */
727028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
728028fa281SKalle Valo
729028fa281SKalle Valo /*
730028fa281SKalle Valo * Enter IQK mode
731028fa281SKalle Valo */
732028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
733028fa281SKalle Valo val32 &= 0x000000ff;
734028fa281SKalle Valo val32 |= 0x80800000;
735028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
736028fa281SKalle Valo
737028fa281SKalle Valo /*
738028fa281SKalle Valo * The vendor driver indicates the USB module is always using
739028fa281SKalle Valo * S0S1 path 1 for the 8723bu. This may be different for 8192eu
740028fa281SKalle Valo */
741028fa281SKalle Valo if (priv->rf_paths > 1)
742028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
743028fa281SKalle Valo else
744028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
745028fa281SKalle Valo
746028fa281SKalle Valo /*
747028fa281SKalle Valo * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
748028fa281SKalle Valo * No trace of this in the 8192eu or 8188eu vendor drivers.
749028fa281SKalle Valo */
750028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
751028fa281SKalle Valo
752028fa281SKalle Valo /* One shot, path A LOK & IQK */
753028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
754028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
755028fa281SKalle Valo
756028fa281SKalle Valo mdelay(1);
757028fa281SKalle Valo
758028fa281SKalle Valo /* Restore Ant Path */
759028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
760028fa281SKalle Valo #ifdef RTL8723BU_BT
761028fa281SKalle Valo /* GNT_BT = 1 */
762028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
763028fa281SKalle Valo #endif
764028fa281SKalle Valo
765028fa281SKalle Valo /*
766028fa281SKalle Valo * Leave IQK mode
767028fa281SKalle Valo */
768028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
769028fa281SKalle Valo val32 &= 0x000000ff;
770028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
771028fa281SKalle Valo
772028fa281SKalle Valo /* Check failed */
773028fa281SKalle Valo reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
774028fa281SKalle Valo reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
775028fa281SKalle Valo reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
776028fa281SKalle Valo
777028fa281SKalle Valo val32 = (reg_e9c >> 16) & 0x3ff;
778028fa281SKalle Valo if (val32 & 0x200)
779028fa281SKalle Valo val32 = 0x400 - val32;
780028fa281SKalle Valo
781028fa281SKalle Valo if (!(reg_eac & BIT(28)) &&
782028fa281SKalle Valo ((reg_e94 & 0x03ff0000) != 0x01420000) &&
783028fa281SKalle Valo ((reg_e9c & 0x03ff0000) != 0x00420000) &&
784028fa281SKalle Valo ((reg_e94 & 0x03ff0000) < 0x01100000) &&
785028fa281SKalle Valo ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
786028fa281SKalle Valo val32 < 0xf)
787028fa281SKalle Valo result |= 0x01;
788028fa281SKalle Valo else /* If TX not OK, ignore RX */
789028fa281SKalle Valo goto out;
790028fa281SKalle Valo
791028fa281SKalle Valo val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
792028fa281SKalle Valo ((reg_e9c & 0x3ff0000) >> 16);
793028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK, val32);
794028fa281SKalle Valo
795028fa281SKalle Valo /*
796028fa281SKalle Valo * Modify RX IQK mode
797028fa281SKalle Valo */
798028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
799028fa281SKalle Valo val32 &= 0x000000ff;
800028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
801028fa281SKalle Valo val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
802028fa281SKalle Valo val32 |= 0x80000;
803028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
804028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
805028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
806028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
807028fa281SKalle Valo
808028fa281SKalle Valo /*
809028fa281SKalle Valo * PA, PAD setting
810028fa281SKalle Valo */
811028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0xf80);
812028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
813028fa281SKalle Valo
814028fa281SKalle Valo /*
815028fa281SKalle Valo * RX IQK setting
816028fa281SKalle Valo */
817028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
818028fa281SKalle Valo
819028fa281SKalle Valo /* path-A IQK setting */
820028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
821028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
822028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
823028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
824028fa281SKalle Valo
825028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
826028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
827028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
828028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
829028fa281SKalle Valo
830028fa281SKalle Valo /* LO calibration setting */
831028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
832028fa281SKalle Valo
833028fa281SKalle Valo /*
834028fa281SKalle Valo * Enter IQK mode
835028fa281SKalle Valo */
836028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
837028fa281SKalle Valo val32 &= 0x000000ff;
838028fa281SKalle Valo val32 |= 0x80800000;
839028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
840028fa281SKalle Valo
841028fa281SKalle Valo if (priv->rf_paths > 1)
842028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
843028fa281SKalle Valo else
844028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
845028fa281SKalle Valo
846028fa281SKalle Valo /*
847028fa281SKalle Valo * Disable BT
848028fa281SKalle Valo */
849028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
850028fa281SKalle Valo
851028fa281SKalle Valo /* One shot, path A LOK & IQK */
852028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
853028fa281SKalle Valo rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
854028fa281SKalle Valo
855028fa281SKalle Valo mdelay(1);
856028fa281SKalle Valo
857028fa281SKalle Valo /* Restore Ant Path */
858028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
859028fa281SKalle Valo #ifdef RTL8723BU_BT
860028fa281SKalle Valo /* GNT_BT = 1 */
861028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
862028fa281SKalle Valo #endif
863028fa281SKalle Valo
864028fa281SKalle Valo /*
865028fa281SKalle Valo * Leave IQK mode
866028fa281SKalle Valo */
867028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
868028fa281SKalle Valo val32 &= 0x000000ff;
869028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
870028fa281SKalle Valo
871028fa281SKalle Valo /* Check failed */
872028fa281SKalle Valo reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
873028fa281SKalle Valo reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
874028fa281SKalle Valo
875028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x780);
876028fa281SKalle Valo
877028fa281SKalle Valo val32 = (reg_eac >> 16) & 0x3ff;
878028fa281SKalle Valo if (val32 & 0x200)
879028fa281SKalle Valo val32 = 0x400 - val32;
880028fa281SKalle Valo
881028fa281SKalle Valo if (!(reg_eac & BIT(27)) &&
882028fa281SKalle Valo ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
883028fa281SKalle Valo ((reg_eac & 0x03ff0000) != 0x00360000) &&
884028fa281SKalle Valo ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
885028fa281SKalle Valo ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
886028fa281SKalle Valo val32 < 0xf)
887028fa281SKalle Valo result |= 0x02;
888028fa281SKalle Valo else /* If TX not OK, ignore RX */
889028fa281SKalle Valo goto out;
890028fa281SKalle Valo out:
891028fa281SKalle Valo return result;
892028fa281SKalle Valo }
893028fa281SKalle Valo
rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv * priv,int result[][8],int t)894028fa281SKalle Valo static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
895028fa281SKalle Valo int result[][8], int t)
896028fa281SKalle Valo {
897028fa281SKalle Valo struct device *dev = &priv->udev->dev;
898028fa281SKalle Valo u32 i, val32;
899028fa281SKalle Valo int path_a_ok /*, path_b_ok */;
900028fa281SKalle Valo int retry = 2;
901028fa281SKalle Valo static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
902028fa281SKalle Valo REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
903028fa281SKalle Valo REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
904028fa281SKalle Valo REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
905028fa281SKalle Valo REG_TX_OFDM_BBON, REG_TX_TO_RX,
906028fa281SKalle Valo REG_TX_TO_TX, REG_RX_CCK,
907028fa281SKalle Valo REG_RX_OFDM, REG_RX_WAIT_RIFS,
908028fa281SKalle Valo REG_RX_TO_RX, REG_STANDBY,
909028fa281SKalle Valo REG_SLEEP, REG_PMPD_ANAEN
910028fa281SKalle Valo };
911028fa281SKalle Valo static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
912028fa281SKalle Valo REG_TXPAUSE, REG_BEACON_CTRL,
913028fa281SKalle Valo REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
914028fa281SKalle Valo };
915028fa281SKalle Valo static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
916028fa281SKalle Valo REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
917028fa281SKalle Valo REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
918028fa281SKalle Valo REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
919028fa281SKalle Valo REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
920028fa281SKalle Valo };
921028fa281SKalle Valo u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
922028fa281SKalle Valo u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
923028fa281SKalle Valo
924028fa281SKalle Valo /*
925028fa281SKalle Valo * Note: IQ calibration must be performed after loading
926028fa281SKalle Valo * PHY_REG.txt , and radio_a, radio_b.txt
927028fa281SKalle Valo */
928028fa281SKalle Valo
929028fa281SKalle Valo if (t == 0) {
930028fa281SKalle Valo /* Save ADDA parameters, turn Path A ADDA on */
931028fa281SKalle Valo rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
932028fa281SKalle Valo RTL8XXXU_ADDA_REGS);
933028fa281SKalle Valo rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
934028fa281SKalle Valo rtl8xxxu_save_regs(priv, iqk_bb_regs,
935028fa281SKalle Valo priv->bb_backup, RTL8XXXU_BB_REGS);
936028fa281SKalle Valo }
937028fa281SKalle Valo
938028fa281SKalle Valo rtl8xxxu_path_adda_on(priv, adda_regs, true);
939028fa281SKalle Valo
940028fa281SKalle Valo /* MAC settings */
941028fa281SKalle Valo rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
942028fa281SKalle Valo
943028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
944028fa281SKalle Valo val32 |= 0x0f000000;
945028fa281SKalle Valo rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
946028fa281SKalle Valo
947028fa281SKalle Valo rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
948028fa281SKalle Valo rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
949028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
950028fa281SKalle Valo
951028fa281SKalle Valo /*
952028fa281SKalle Valo * RX IQ calibration setting for 8723B D cut large current issue
953028fa281SKalle Valo * when leaving IPS
954028fa281SKalle Valo */
955028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
956028fa281SKalle Valo val32 &= 0x000000ff;
957028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
958028fa281SKalle Valo
959028fa281SKalle Valo val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
960028fa281SKalle Valo val32 |= 0x80000;
961028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
962028fa281SKalle Valo
963028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
964028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
965028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
966028fa281SKalle Valo
967028fa281SKalle Valo val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
968028fa281SKalle Valo val32 |= 0x20;
969028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
970028fa281SKalle Valo
971028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
972028fa281SKalle Valo
973028fa281SKalle Valo for (i = 0; i < retry; i++) {
974028fa281SKalle Valo path_a_ok = rtl8723bu_iqk_path_a(priv);
975028fa281SKalle Valo if (path_a_ok == 0x01) {
976028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
977028fa281SKalle Valo val32 &= 0x000000ff;
978028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
979028fa281SKalle Valo
980028fa281SKalle Valo val32 = rtl8xxxu_read32(priv,
981028fa281SKalle Valo REG_TX_POWER_BEFORE_IQK_A);
982028fa281SKalle Valo result[t][0] = (val32 >> 16) & 0x3ff;
983028fa281SKalle Valo val32 = rtl8xxxu_read32(priv,
984028fa281SKalle Valo REG_TX_POWER_AFTER_IQK_A);
985028fa281SKalle Valo result[t][1] = (val32 >> 16) & 0x3ff;
986028fa281SKalle Valo
987028fa281SKalle Valo break;
988028fa281SKalle Valo }
989028fa281SKalle Valo }
990028fa281SKalle Valo
991028fa281SKalle Valo if (!path_a_ok)
992028fa281SKalle Valo dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
993028fa281SKalle Valo
994028fa281SKalle Valo for (i = 0; i < retry; i++) {
995028fa281SKalle Valo path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
996028fa281SKalle Valo if (path_a_ok == 0x03) {
997028fa281SKalle Valo val32 = rtl8xxxu_read32(priv,
998028fa281SKalle Valo REG_RX_POWER_BEFORE_IQK_A_2);
999028fa281SKalle Valo result[t][2] = (val32 >> 16) & 0x3ff;
1000028fa281SKalle Valo val32 = rtl8xxxu_read32(priv,
1001028fa281SKalle Valo REG_RX_POWER_AFTER_IQK_A_2);
1002028fa281SKalle Valo result[t][3] = (val32 >> 16) & 0x3ff;
1003028fa281SKalle Valo
1004028fa281SKalle Valo break;
1005028fa281SKalle Valo }
1006028fa281SKalle Valo }
1007028fa281SKalle Valo
1008028fa281SKalle Valo if (!path_a_ok)
1009028fa281SKalle Valo dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
1010028fa281SKalle Valo
1011028fa281SKalle Valo if (priv->tx_paths > 1) {
1012028fa281SKalle Valo #if 1
1013028fa281SKalle Valo dev_warn(dev, "%s: Path B not supported\n", __func__);
1014028fa281SKalle Valo #else
1015028fa281SKalle Valo
1016028fa281SKalle Valo /*
1017028fa281SKalle Valo * Path A into standby
1018028fa281SKalle Valo */
1019028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1020028fa281SKalle Valo val32 &= 0x000000ff;
1021028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1022028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1023028fa281SKalle Valo
1024028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1025028fa281SKalle Valo val32 &= 0x000000ff;
1026028fa281SKalle Valo val32 |= 0x80800000;
1027028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1028028fa281SKalle Valo
1029028fa281SKalle Valo /* Turn Path B ADDA on */
1030028fa281SKalle Valo rtl8xxxu_path_adda_on(priv, adda_regs, false);
1031028fa281SKalle Valo
1032028fa281SKalle Valo for (i = 0; i < retry; i++) {
1033028fa281SKalle Valo path_b_ok = rtl8xxxu_iqk_path_b(priv);
1034028fa281SKalle Valo if (path_b_ok == 0x03) {
1035028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1036028fa281SKalle Valo result[t][4] = (val32 >> 16) & 0x3ff;
1037028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1038028fa281SKalle Valo result[t][5] = (val32 >> 16) & 0x3ff;
1039028fa281SKalle Valo break;
1040028fa281SKalle Valo }
1041028fa281SKalle Valo }
1042028fa281SKalle Valo
1043028fa281SKalle Valo if (!path_b_ok)
1044028fa281SKalle Valo dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1045028fa281SKalle Valo
1046028fa281SKalle Valo for (i = 0; i < retry; i++) {
1047028fa281SKalle Valo path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
1048028fa281SKalle Valo if (path_a_ok == 0x03) {
1049028fa281SKalle Valo val32 = rtl8xxxu_read32(priv,
1050028fa281SKalle Valo REG_RX_POWER_BEFORE_IQK_B_2);
1051028fa281SKalle Valo result[t][6] = (val32 >> 16) & 0x3ff;
1052028fa281SKalle Valo val32 = rtl8xxxu_read32(priv,
1053028fa281SKalle Valo REG_RX_POWER_AFTER_IQK_B_2);
1054028fa281SKalle Valo result[t][7] = (val32 >> 16) & 0x3ff;
1055028fa281SKalle Valo break;
1056028fa281SKalle Valo }
1057028fa281SKalle Valo }
1058028fa281SKalle Valo
1059028fa281SKalle Valo if (!path_b_ok)
1060028fa281SKalle Valo dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1061028fa281SKalle Valo #endif
1062028fa281SKalle Valo }
1063028fa281SKalle Valo
1064028fa281SKalle Valo /* Back to BB mode, load original value */
1065028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1066028fa281SKalle Valo val32 &= 0x000000ff;
1067028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1068028fa281SKalle Valo
1069028fa281SKalle Valo if (t) {
1070028fa281SKalle Valo /* Reload ADDA power saving parameters */
1071028fa281SKalle Valo rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1072028fa281SKalle Valo RTL8XXXU_ADDA_REGS);
1073028fa281SKalle Valo
1074028fa281SKalle Valo /* Reload MAC parameters */
1075028fa281SKalle Valo rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1076028fa281SKalle Valo
1077028fa281SKalle Valo /* Reload BB parameters */
1078028fa281SKalle Valo rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1079028fa281SKalle Valo priv->bb_backup, RTL8XXXU_BB_REGS);
1080028fa281SKalle Valo
1081028fa281SKalle Valo /* Restore RX initial gain */
1082028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1083028fa281SKalle Valo val32 &= 0xffffff00;
1084028fa281SKalle Valo rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1085028fa281SKalle Valo rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1086028fa281SKalle Valo
1087028fa281SKalle Valo if (priv->tx_paths > 1) {
1088028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1089028fa281SKalle Valo val32 &= 0xffffff00;
1090028fa281SKalle Valo rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1091028fa281SKalle Valo val32 | 0x50);
1092028fa281SKalle Valo rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1093028fa281SKalle Valo val32 | xb_agc);
1094028fa281SKalle Valo }
1095028fa281SKalle Valo
1096028fa281SKalle Valo /* Load 0xe30 IQC default value */
1097028fa281SKalle Valo rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1098028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1099028fa281SKalle Valo }
1100028fa281SKalle Valo }
1101028fa281SKalle Valo
rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv * priv)1102028fa281SKalle Valo static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1103028fa281SKalle Valo {
1104028fa281SKalle Valo struct device *dev = &priv->udev->dev;
1105028fa281SKalle Valo int result[4][8]; /* last is final result */
1106028fa281SKalle Valo int i, candidate;
1107028fa281SKalle Valo bool path_a_ok, path_b_ok;
1108028fa281SKalle Valo u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1109028fa281SKalle Valo u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1110028fa281SKalle Valo u32 val32, bt_control;
1111028fa281SKalle Valo s32 reg_tmp = 0;
1112028fa281SKalle Valo bool simu;
1113028fa281SKalle Valo
1114028fa281SKalle Valo rtl8xxxu_gen2_prepare_calibrate(priv, 1);
1115028fa281SKalle Valo
1116028fa281SKalle Valo memset(result, 0, sizeof(result));
1117028fa281SKalle Valo candidate = -1;
1118028fa281SKalle Valo
1119028fa281SKalle Valo path_a_ok = false;
1120028fa281SKalle Valo path_b_ok = false;
1121028fa281SKalle Valo
1122028fa281SKalle Valo bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
1123028fa281SKalle Valo
1124028fa281SKalle Valo for (i = 0; i < 3; i++) {
1125028fa281SKalle Valo rtl8723bu_phy_iqcalibrate(priv, result, i);
1126028fa281SKalle Valo
1127028fa281SKalle Valo if (i == 1) {
1128028fa281SKalle Valo simu = rtl8xxxu_gen2_simularity_compare(priv,
1129028fa281SKalle Valo result, 0, 1);
1130028fa281SKalle Valo if (simu) {
1131028fa281SKalle Valo candidate = 0;
1132028fa281SKalle Valo break;
1133028fa281SKalle Valo }
1134028fa281SKalle Valo }
1135028fa281SKalle Valo
1136028fa281SKalle Valo if (i == 2) {
1137028fa281SKalle Valo simu = rtl8xxxu_gen2_simularity_compare(priv,
1138028fa281SKalle Valo result, 0, 2);
1139028fa281SKalle Valo if (simu) {
1140028fa281SKalle Valo candidate = 0;
1141028fa281SKalle Valo break;
1142028fa281SKalle Valo }
1143028fa281SKalle Valo
1144028fa281SKalle Valo simu = rtl8xxxu_gen2_simularity_compare(priv,
1145028fa281SKalle Valo result, 1, 2);
1146028fa281SKalle Valo if (simu) {
1147028fa281SKalle Valo candidate = 1;
1148028fa281SKalle Valo } else {
1149028fa281SKalle Valo for (i = 0; i < 8; i++)
1150028fa281SKalle Valo reg_tmp += result[3][i];
1151028fa281SKalle Valo
1152028fa281SKalle Valo if (reg_tmp)
1153028fa281SKalle Valo candidate = 3;
1154028fa281SKalle Valo else
1155028fa281SKalle Valo candidate = -1;
1156028fa281SKalle Valo }
1157028fa281SKalle Valo }
1158028fa281SKalle Valo }
1159028fa281SKalle Valo
1160028fa281SKalle Valo for (i = 0; i < 4; i++) {
1161028fa281SKalle Valo reg_e94 = result[i][0];
1162028fa281SKalle Valo reg_e9c = result[i][1];
1163028fa281SKalle Valo reg_ea4 = result[i][2];
1164028fa281SKalle Valo reg_eac = result[i][3];
1165028fa281SKalle Valo reg_eb4 = result[i][4];
1166028fa281SKalle Valo reg_ebc = result[i][5];
1167028fa281SKalle Valo reg_ec4 = result[i][6];
1168028fa281SKalle Valo reg_ecc = result[i][7];
1169028fa281SKalle Valo }
1170028fa281SKalle Valo
1171028fa281SKalle Valo if (candidate >= 0) {
1172028fa281SKalle Valo reg_e94 = result[candidate][0];
1173028fa281SKalle Valo priv->rege94 = reg_e94;
1174028fa281SKalle Valo reg_e9c = result[candidate][1];
1175028fa281SKalle Valo priv->rege9c = reg_e9c;
1176028fa281SKalle Valo reg_ea4 = result[candidate][2];
1177028fa281SKalle Valo reg_eac = result[candidate][3];
1178028fa281SKalle Valo reg_eb4 = result[candidate][4];
1179028fa281SKalle Valo priv->regeb4 = reg_eb4;
1180028fa281SKalle Valo reg_ebc = result[candidate][5];
1181028fa281SKalle Valo priv->regebc = reg_ebc;
1182028fa281SKalle Valo reg_ec4 = result[candidate][6];
1183028fa281SKalle Valo reg_ecc = result[candidate][7];
1184028fa281SKalle Valo dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1185028fa281SKalle Valo dev_dbg(dev,
1186028fa281SKalle Valo "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1187028fa281SKalle Valo __func__, reg_e94, reg_e9c,
1188028fa281SKalle Valo reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1189028fa281SKalle Valo path_a_ok = true;
1190028fa281SKalle Valo path_b_ok = true;
1191028fa281SKalle Valo } else {
1192028fa281SKalle Valo reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1193028fa281SKalle Valo reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1194028fa281SKalle Valo }
1195028fa281SKalle Valo
1196028fa281SKalle Valo if (reg_e94 && candidate >= 0)
1197028fa281SKalle Valo rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1198028fa281SKalle Valo candidate, (reg_ea4 == 0));
1199028fa281SKalle Valo
1200028fa281SKalle Valo if (priv->tx_paths > 1 && reg_eb4)
1201028fa281SKalle Valo rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1202028fa281SKalle Valo candidate, (reg_ec4 == 0));
1203028fa281SKalle Valo
1204028fa281SKalle Valo rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1205028fa281SKalle Valo priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1206028fa281SKalle Valo
1207028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
1208028fa281SKalle Valo
1209028fa281SKalle Valo val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
1210028fa281SKalle Valo val32 |= 0x80000;
1211028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
1212028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
1213028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
1214028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
1215028fa281SKalle Valo val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
1216028fa281SKalle Valo val32 |= 0x20;
1217028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
1218028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
1219028fa281SKalle Valo
1220028fa281SKalle Valo if (priv->rf_paths > 1)
1221028fa281SKalle Valo dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__);
1222028fa281SKalle Valo
1223028fa281SKalle Valo rtl8xxxu_gen2_prepare_calibrate(priv, 0);
1224028fa281SKalle Valo }
1225028fa281SKalle Valo
rtl8723bu_active_to_emu(struct rtl8xxxu_priv * priv)1226028fa281SKalle Valo static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
1227028fa281SKalle Valo {
1228028fa281SKalle Valo u8 val8;
1229028fa281SKalle Valo u16 val16;
1230028fa281SKalle Valo u32 val32;
1231028fa281SKalle Valo int count, ret = 0;
1232028fa281SKalle Valo
1233028fa281SKalle Valo /* Turn off RF */
1234028fa281SKalle Valo rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
1235028fa281SKalle Valo
1236028fa281SKalle Valo /* Enable rising edge triggering interrupt */
1237028fa281SKalle Valo val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
1238028fa281SKalle Valo val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
1239028fa281SKalle Valo rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
1240028fa281SKalle Valo
1241028fa281SKalle Valo /* Release WLON reset 0x04[16]= 1*/
1242028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1243028fa281SKalle Valo val32 |= APS_FSMCO_WLON_RESET;
1244028fa281SKalle Valo rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1245028fa281SKalle Valo
1246028fa281SKalle Valo /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1247028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1248028fa281SKalle Valo val8 |= BIT(1);
1249028fa281SKalle Valo rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1250028fa281SKalle Valo
1251028fa281SKalle Valo for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1252028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1253028fa281SKalle Valo if ((val8 & BIT(1)) == 0)
1254028fa281SKalle Valo break;
1255028fa281SKalle Valo udelay(10);
1256028fa281SKalle Valo }
1257028fa281SKalle Valo
1258028fa281SKalle Valo if (!count) {
1259028fa281SKalle Valo dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1260028fa281SKalle Valo __func__);
1261028fa281SKalle Valo ret = -EBUSY;
1262028fa281SKalle Valo goto exit;
1263028fa281SKalle Valo }
1264028fa281SKalle Valo
1265028fa281SKalle Valo /* Enable BT control XTAL setting */
1266028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1267028fa281SKalle Valo val8 &= ~AFE_MISC_WL_XTAL_CTRL;
1268028fa281SKalle Valo rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1269028fa281SKalle Valo
1270028fa281SKalle Valo /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
1271028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1272028fa281SKalle Valo val8 |= SYS_ISO_ANALOG_IPS;
1273028fa281SKalle Valo rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1274028fa281SKalle Valo
1275028fa281SKalle Valo /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
1276028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1277028fa281SKalle Valo val8 &= ~LDOA15_ENABLE;
1278028fa281SKalle Valo rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1279028fa281SKalle Valo
1280028fa281SKalle Valo exit:
1281028fa281SKalle Valo return ret;
1282028fa281SKalle Valo }
1283028fa281SKalle Valo
rtl8723b_emu_to_active(struct rtl8xxxu_priv * priv)1284028fa281SKalle Valo static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
1285028fa281SKalle Valo {
1286028fa281SKalle Valo u8 val8;
1287028fa281SKalle Valo u32 val32;
1288028fa281SKalle Valo int count, ret = 0;
1289028fa281SKalle Valo
1290028fa281SKalle Valo /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
1291028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1292028fa281SKalle Valo val8 |= LDOA15_ENABLE;
1293028fa281SKalle Valo rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1294028fa281SKalle Valo
1295028fa281SKalle Valo /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
1296028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, 0x0067);
1297028fa281SKalle Valo val8 &= ~BIT(4);
1298028fa281SKalle Valo rtl8xxxu_write8(priv, 0x0067, val8);
1299028fa281SKalle Valo
1300028fa281SKalle Valo mdelay(1);
1301028fa281SKalle Valo
1302028fa281SKalle Valo /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
1303028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1304028fa281SKalle Valo val8 &= ~SYS_ISO_ANALOG_IPS;
1305028fa281SKalle Valo rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1306028fa281SKalle Valo
1307028fa281SKalle Valo /* Disable SW LPS 0x04[10]= 0 */
1308028fa281SKalle Valo val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
1309028fa281SKalle Valo val32 &= ~APS_FSMCO_SW_LPS;
1310028fa281SKalle Valo rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1311028fa281SKalle Valo
1312028fa281SKalle Valo /* Wait until 0x04[17] = 1 power ready */
1313028fa281SKalle Valo for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1314028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1315028fa281SKalle Valo if (val32 & BIT(17))
1316028fa281SKalle Valo break;
1317028fa281SKalle Valo
1318028fa281SKalle Valo udelay(10);
1319028fa281SKalle Valo }
1320028fa281SKalle Valo
1321028fa281SKalle Valo if (!count) {
1322028fa281SKalle Valo ret = -EBUSY;
1323028fa281SKalle Valo goto exit;
1324028fa281SKalle Valo }
1325028fa281SKalle Valo
1326028fa281SKalle Valo /* We should be able to optimize the following three entries into one */
1327028fa281SKalle Valo
1328028fa281SKalle Valo /* Release WLON reset 0x04[16]= 1*/
1329028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1330028fa281SKalle Valo val32 |= APS_FSMCO_WLON_RESET;
1331028fa281SKalle Valo rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1332028fa281SKalle Valo
1333028fa281SKalle Valo /* Disable HWPDN 0x04[15]= 0*/
1334028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1335028fa281SKalle Valo val32 &= ~APS_FSMCO_HW_POWERDOWN;
1336028fa281SKalle Valo rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1337028fa281SKalle Valo
1338028fa281SKalle Valo /* Disable WL suspend*/
1339028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1340028fa281SKalle Valo val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
1341028fa281SKalle Valo rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1342028fa281SKalle Valo
1343028fa281SKalle Valo /* Set, then poll until 0 */
1344028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1345028fa281SKalle Valo val32 |= APS_FSMCO_MAC_ENABLE;
1346028fa281SKalle Valo rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1347028fa281SKalle Valo
1348028fa281SKalle Valo for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1349028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1350028fa281SKalle Valo if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1351028fa281SKalle Valo ret = 0;
1352028fa281SKalle Valo break;
1353028fa281SKalle Valo }
1354028fa281SKalle Valo udelay(10);
1355028fa281SKalle Valo }
1356028fa281SKalle Valo
1357028fa281SKalle Valo if (!count) {
1358028fa281SKalle Valo ret = -EBUSY;
1359028fa281SKalle Valo goto exit;
1360028fa281SKalle Valo }
1361028fa281SKalle Valo
1362028fa281SKalle Valo /* Enable WL control XTAL setting */
1363028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1364028fa281SKalle Valo val8 |= AFE_MISC_WL_XTAL_CTRL;
1365028fa281SKalle Valo rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1366028fa281SKalle Valo
1367028fa281SKalle Valo /* Enable falling edge triggering interrupt */
1368028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
1369028fa281SKalle Valo val8 |= BIT(1);
1370028fa281SKalle Valo rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
1371028fa281SKalle Valo
1372028fa281SKalle Valo /* Enable GPIO9 interrupt mode */
1373028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
1374028fa281SKalle Valo val8 |= BIT(1);
1375028fa281SKalle Valo rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
1376028fa281SKalle Valo
1377028fa281SKalle Valo /* Enable GPIO9 input mode */
1378028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
1379028fa281SKalle Valo val8 &= ~BIT(1);
1380028fa281SKalle Valo rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
1381028fa281SKalle Valo
1382028fa281SKalle Valo /* Enable HSISR GPIO[C:0] interrupt */
1383028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_HSIMR);
1384028fa281SKalle Valo val8 |= BIT(0);
1385028fa281SKalle Valo rtl8xxxu_write8(priv, REG_HSIMR, val8);
1386028fa281SKalle Valo
1387028fa281SKalle Valo /* Enable HSISR GPIO9 interrupt */
1388028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
1389028fa281SKalle Valo val8 |= BIT(1);
1390028fa281SKalle Valo rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
1391028fa281SKalle Valo
1392028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
1393028fa281SKalle Valo val8 |= MULTI_WIFI_HW_ROF_EN;
1394028fa281SKalle Valo rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
1395028fa281SKalle Valo
1396028fa281SKalle Valo /* For GPIO9 internal pull high setting BIT(14) */
1397028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
1398028fa281SKalle Valo val8 |= BIT(6);
1399028fa281SKalle Valo rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
1400028fa281SKalle Valo
1401028fa281SKalle Valo exit:
1402028fa281SKalle Valo return ret;
1403028fa281SKalle Valo }
1404028fa281SKalle Valo
rtl8723bu_power_on(struct rtl8xxxu_priv * priv)1405028fa281SKalle Valo static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
1406028fa281SKalle Valo {
1407028fa281SKalle Valo u8 val8;
1408028fa281SKalle Valo u16 val16;
1409028fa281SKalle Valo u32 val32;
1410028fa281SKalle Valo int ret;
1411028fa281SKalle Valo
1412028fa281SKalle Valo rtl8xxxu_disabled_to_emu(priv);
1413028fa281SKalle Valo
1414028fa281SKalle Valo ret = rtl8723b_emu_to_active(priv);
1415028fa281SKalle Valo if (ret)
1416028fa281SKalle Valo goto exit;
1417028fa281SKalle Valo
1418028fa281SKalle Valo /*
1419028fa281SKalle Valo * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1420028fa281SKalle Valo * Set CR bit10 to enable 32k calibration.
1421028fa281SKalle Valo */
1422028fa281SKalle Valo val16 = rtl8xxxu_read16(priv, REG_CR);
1423028fa281SKalle Valo val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1424028fa281SKalle Valo CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1425028fa281SKalle Valo CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1426028fa281SKalle Valo CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1427028fa281SKalle Valo CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1428028fa281SKalle Valo rtl8xxxu_write16(priv, REG_CR, val16);
1429028fa281SKalle Valo
1430028fa281SKalle Valo /*
1431028fa281SKalle Valo * BT coexist power on settings. This is identical for 1 and 2
1432028fa281SKalle Valo * antenna parts.
1433028fa281SKalle Valo */
1434028fa281SKalle Valo rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
1435028fa281SKalle Valo
1436028fa281SKalle Valo val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1437028fa281SKalle Valo val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
1438028fa281SKalle Valo rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1439028fa281SKalle Valo
1440028fa281SKalle Valo rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
1441028fa281SKalle Valo rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1442028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
1443028fa281SKalle Valo /* Antenna inverse */
1444028fa281SKalle Valo rtl8xxxu_write8(priv, 0xfe08, 0x01);
1445028fa281SKalle Valo
1446028fa281SKalle Valo val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
1447028fa281SKalle Valo val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1448028fa281SKalle Valo rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
1449028fa281SKalle Valo
1450028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1451028fa281SKalle Valo val32 |= LEDCFG0_DPDT_SELECT;
1452028fa281SKalle Valo rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1453028fa281SKalle Valo
1454028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1455028fa281SKalle Valo val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
1456028fa281SKalle Valo rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1457028fa281SKalle Valo exit:
1458028fa281SKalle Valo return ret;
1459028fa281SKalle Valo }
1460028fa281SKalle Valo
rtl8723bu_power_off(struct rtl8xxxu_priv * priv)1461028fa281SKalle Valo static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
1462028fa281SKalle Valo {
1463028fa281SKalle Valo u8 val8;
1464028fa281SKalle Valo u16 val16;
1465028fa281SKalle Valo
1466028fa281SKalle Valo rtl8xxxu_flush_fifo(priv);
1467028fa281SKalle Valo
1468028fa281SKalle Valo /*
1469028fa281SKalle Valo * Disable TX report timer
1470028fa281SKalle Valo */
1471028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1472028fa281SKalle Valo val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1473028fa281SKalle Valo rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1474028fa281SKalle Valo
1475028fa281SKalle Valo rtl8xxxu_write8(priv, REG_CR, 0x0000);
1476028fa281SKalle Valo
1477028fa281SKalle Valo rtl8xxxu_active_to_lps(priv);
1478028fa281SKalle Valo
1479028fa281SKalle Valo /* Reset Firmware if running in RAM */
1480028fa281SKalle Valo if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1481028fa281SKalle Valo rtl8xxxu_firmware_self_reset(priv);
1482028fa281SKalle Valo
1483028fa281SKalle Valo /* Reset MCU */
1484028fa281SKalle Valo val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1485028fa281SKalle Valo val16 &= ~SYS_FUNC_CPU_ENABLE;
1486028fa281SKalle Valo rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1487028fa281SKalle Valo
1488028fa281SKalle Valo /* Reset MCU ready status */
1489028fa281SKalle Valo rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1490028fa281SKalle Valo
1491028fa281SKalle Valo rtl8723bu_active_to_emu(priv);
1492028fa281SKalle Valo
1493028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1494028fa281SKalle Valo val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */
1495028fa281SKalle Valo rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1496028fa281SKalle Valo
1497028fa281SKalle Valo /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
1498028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
1499028fa281SKalle Valo val8 |= BIT(0);
1500028fa281SKalle Valo rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
1501028fa281SKalle Valo }
1502028fa281SKalle Valo
rtl8723b_enable_rf(struct rtl8xxxu_priv * priv)1503028fa281SKalle Valo static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
1504028fa281SKalle Valo {
1505028fa281SKalle Valo struct h2c_cmd h2c;
1506028fa281SKalle Valo u32 val32;
1507028fa281SKalle Valo u8 val8;
1508028fa281SKalle Valo
1509028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1510028fa281SKalle Valo val32 |= (BIT(22) | BIT(23));
1511028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1512028fa281SKalle Valo
1513028fa281SKalle Valo /*
1514028fa281SKalle Valo * No indication anywhere as to what 0x0790 does. The 2 antenna
1515028fa281SKalle Valo * vendor code preserves bits 6-7 here.
1516028fa281SKalle Valo */
1517028fa281SKalle Valo rtl8xxxu_write8(priv, 0x0790, 0x05);
1518028fa281SKalle Valo /*
1519028fa281SKalle Valo * 0x0778 seems to be related to enabling the number of antennas
1520028fa281SKalle Valo * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
1521028fa281SKalle Valo * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
1522028fa281SKalle Valo */
1523028fa281SKalle Valo rtl8xxxu_write8(priv, 0x0778, 0x01);
1524028fa281SKalle Valo
1525028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1526028fa281SKalle Valo val8 |= BIT(5);
1527028fa281SKalle Valo rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1528028fa281SKalle Valo
1529028fa281SKalle Valo rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
1530028fa281SKalle Valo
1531028fa281SKalle Valo rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
1532028fa281SKalle Valo
1533028fa281SKalle Valo /*
1534028fa281SKalle Valo * Set BT grant to low
1535028fa281SKalle Valo */
1536028fa281SKalle Valo memset(&h2c, 0, sizeof(struct h2c_cmd));
1537028fa281SKalle Valo h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
1538028fa281SKalle Valo h2c.bt_grant.data = 0;
1539028fa281SKalle Valo rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
1540028fa281SKalle Valo
1541028fa281SKalle Valo /*
1542028fa281SKalle Valo * WLAN action by PTA
1543028fa281SKalle Valo */
1544028fa281SKalle Valo rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c);
1545028fa281SKalle Valo
1546028fa281SKalle Valo /*
1547028fa281SKalle Valo * BT select S0/S1 controlled by WiFi
1548028fa281SKalle Valo */
1549028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, 0x0067);
1550028fa281SKalle Valo val8 |= BIT(5);
1551028fa281SKalle Valo rtl8xxxu_write8(priv, 0x0067, val8);
1552028fa281SKalle Valo
1553028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1554028fa281SKalle Valo val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1555028fa281SKalle Valo rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1556028fa281SKalle Valo
1557028fa281SKalle Valo /*
1558028fa281SKalle Valo * Bits 6/7 are marked in/out ... but for what?
1559028fa281SKalle Valo */
1560028fa281SKalle Valo rtl8xxxu_write8(priv, 0x0974, 0xff);
1561028fa281SKalle Valo
1562028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1563028fa281SKalle Valo val32 |= (BIT(0) | BIT(1));
1564028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1565028fa281SKalle Valo
1566028fa281SKalle Valo rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1567028fa281SKalle Valo
1568028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1569028fa281SKalle Valo val32 &= ~BIT(24);
1570028fa281SKalle Valo val32 |= BIT(23);
1571028fa281SKalle Valo rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1572028fa281SKalle Valo
1573028fa281SKalle Valo /*
1574028fa281SKalle Valo * Fix external switch Main->S1, Aux->S0
1575028fa281SKalle Valo */
1576028fa281SKalle Valo val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1577028fa281SKalle Valo val8 &= ~BIT(0);
1578028fa281SKalle Valo rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1579028fa281SKalle Valo
1580028fa281SKalle Valo memset(&h2c, 0, sizeof(struct h2c_cmd));
1581028fa281SKalle Valo h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
1582028fa281SKalle Valo h2c.ant_sel_rsv.ant_inverse = 1;
1583028fa281SKalle Valo h2c.ant_sel_rsv.int_switch_type = 0;
1584028fa281SKalle Valo rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
1585028fa281SKalle Valo
1586028fa281SKalle Valo /*
1587028fa281SKalle Valo * Different settings per different antenna position.
1588028fa281SKalle Valo * Antenna Position: | Normal Inverse
1589028fa281SKalle Valo * --------------------------------------------------
1590028fa281SKalle Valo * Antenna switch to BT: | 0x280, 0x00
1591028fa281SKalle Valo * Antenna switch to WiFi: | 0x0, 0x280
1592028fa281SKalle Valo * Antenna switch to PTA: | 0x200, 0x80
1593028fa281SKalle Valo */
1594028fa281SKalle Valo rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80);
1595028fa281SKalle Valo
1596028fa281SKalle Valo /*
1597028fa281SKalle Valo * Software control, antenna at WiFi side
1598028fa281SKalle Valo */
1599028fa281SKalle Valo rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
1600028fa281SKalle Valo
1601028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
1602028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
1603028fa281SKalle Valo rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
1604028fa281SKalle Valo rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
1605028fa281SKalle Valo
1606028fa281SKalle Valo memset(&h2c, 0, sizeof(struct h2c_cmd));
1607028fa281SKalle Valo h2c.bt_info.cmd = H2C_8723B_BT_INFO;
1608028fa281SKalle Valo h2c.bt_info.data = BIT(0);
1609028fa281SKalle Valo rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
1610028fa281SKalle Valo
1611028fa281SKalle Valo memset(&h2c, 0, sizeof(struct h2c_cmd));
1612028fa281SKalle Valo h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
1613028fa281SKalle Valo h2c.ignore_wlan.data = 0;
1614028fa281SKalle Valo rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
1615028fa281SKalle Valo }
1616028fa281SKalle Valo
rtl8723bu_init_aggregation(struct rtl8xxxu_priv * priv)1617028fa281SKalle Valo static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
1618028fa281SKalle Valo {
1619028fa281SKalle Valo u32 agg_rx;
1620028fa281SKalle Valo u8 agg_ctrl;
1621028fa281SKalle Valo
1622028fa281SKalle Valo /*
1623028fa281SKalle Valo * For now simply disable RX aggregation
1624028fa281SKalle Valo */
1625028fa281SKalle Valo agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
1626028fa281SKalle Valo agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
1627028fa281SKalle Valo
1628028fa281SKalle Valo agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
1629028fa281SKalle Valo agg_rx &= ~RXDMA_USB_AGG_ENABLE;
1630028fa281SKalle Valo agg_rx &= ~0xff0f;
1631028fa281SKalle Valo
1632028fa281SKalle Valo rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
1633028fa281SKalle Valo rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
1634028fa281SKalle Valo }
1635028fa281SKalle Valo
rtl8723bu_init_statistics(struct rtl8xxxu_priv * priv)1636028fa281SKalle Valo static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
1637028fa281SKalle Valo {
1638028fa281SKalle Valo u32 val32;
1639028fa281SKalle Valo
1640028fa281SKalle Valo /* Time duration for NHM unit: 4us, 0x2710=40ms */
1641028fa281SKalle Valo rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
1642028fa281SKalle Valo rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
1643028fa281SKalle Valo rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
1644028fa281SKalle Valo rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
1645028fa281SKalle Valo /* TH8 */
1646028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1647028fa281SKalle Valo val32 |= 0xff;
1648028fa281SKalle Valo rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1649028fa281SKalle Valo /* Enable CCK */
1650028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
1651028fa281SKalle Valo val32 |= BIT(8) | BIT(9) | BIT(10);
1652028fa281SKalle Valo rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
1653028fa281SKalle Valo /* Max power amongst all RX antennas */
1654028fa281SKalle Valo val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
1655028fa281SKalle Valo val32 |= BIT(7);
1656028fa281SKalle Valo rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
1657028fa281SKalle Valo }
1658028fa281SKalle Valo
rtl8723b_cck_rssi(struct rtl8xxxu_priv * priv,struct rtl8723au_phy_stats * phy_stats)1659028fa281SKalle Valo static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)
1660028fa281SKalle Valo {
1661028fa281SKalle Valo u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
1662028fa281SKalle Valo s8 rx_pwr_all = 0x00;
1663028fa281SKalle Valo u8 vga_idx, lna_idx;
1664028fa281SKalle Valo
1665028fa281SKalle Valo lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK);
1666028fa281SKalle Valo vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK);
1667028fa281SKalle Valo
1668028fa281SKalle Valo switch (lna_idx) {
1669028fa281SKalle Valo case 6:
1670028fa281SKalle Valo rx_pwr_all = -34 - (2 * vga_idx);
1671028fa281SKalle Valo break;
1672028fa281SKalle Valo case 4:
1673028fa281SKalle Valo rx_pwr_all = -14 - (2 * vga_idx);
1674028fa281SKalle Valo break;
1675028fa281SKalle Valo case 1:
1676028fa281SKalle Valo rx_pwr_all = 6 - (2 * vga_idx);
1677028fa281SKalle Valo break;
1678028fa281SKalle Valo case 0:
1679028fa281SKalle Valo rx_pwr_all = 16 - (2 * vga_idx);
1680028fa281SKalle Valo break;
1681028fa281SKalle Valo default:
1682028fa281SKalle Valo break;
1683028fa281SKalle Valo }
1684028fa281SKalle Valo
1685028fa281SKalle Valo return rx_pwr_all;
1686028fa281SKalle Valo }
1687028fa281SKalle Valo
rtl8723bu_led_brightness_set(struct led_classdev * led_cdev,enum led_brightness brightness)1688028fa281SKalle Valo static int rtl8723bu_led_brightness_set(struct led_classdev *led_cdev,
1689028fa281SKalle Valo enum led_brightness brightness)
1690028fa281SKalle Valo {
1691028fa281SKalle Valo struct rtl8xxxu_priv *priv = container_of(led_cdev,
1692028fa281SKalle Valo struct rtl8xxxu_priv,
1693028fa281SKalle Valo led_cdev);
1694028fa281SKalle Valo u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2);
1695028fa281SKalle Valo
1696028fa281SKalle Valo ledcfg &= LEDCFG2_DPDT_SELECT;
1697028fa281SKalle Valo
1698028fa281SKalle Valo if (brightness == LED_OFF)
1699028fa281SKalle Valo ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE;
1700028fa281SKalle Valo else if (brightness == LED_ON)
1701028fa281SKalle Valo ledcfg |= LEDCFG2_SW_LED_CONTROL;
1702028fa281SKalle Valo else if (brightness == RTL8XXXU_HW_LED_CONTROL)
1703028fa281SKalle Valo ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE;
1704028fa281SKalle Valo
1705028fa281SKalle Valo rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg);
1706028fa281SKalle Valo
1707028fa281SKalle Valo return 0;
1708028fa281SKalle Valo }
1709028fa281SKalle Valo
1710028fa281SKalle Valo struct rtl8xxxu_fileops rtl8723bu_fops = {
1711028fa281SKalle Valo .identify_chip = rtl8723bu_identify_chip,
1712028fa281SKalle Valo .parse_efuse = rtl8723bu_parse_efuse,
1713028fa281SKalle Valo .load_firmware = rtl8723bu_load_firmware,
1714028fa281SKalle Valo .power_on = rtl8723bu_power_on,
1715028fa281SKalle Valo .power_off = rtl8723bu_power_off,
1716028fa281SKalle Valo .read_efuse = rtl8xxxu_read_efuse,
1717028fa281SKalle Valo .reset_8051 = rtl8723bu_reset_8051,
1718028fa281SKalle Valo .llt_init = rtl8xxxu_auto_llt_table,
1719028fa281SKalle Valo .init_phy_bb = rtl8723bu_init_phy_bb,
1720028fa281SKalle Valo .init_phy_rf = rtl8723bu_init_phy_rf,
1721028fa281SKalle Valo .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
1722028fa281SKalle Valo .phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
1723028fa281SKalle Valo .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
1724028fa281SKalle Valo .config_channel = rtl8xxxu_gen2_config_channel,
1725028fa281SKalle Valo .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1726028fa281SKalle Valo .parse_phystats = rtl8723au_rx_parse_phystats,
1727028fa281SKalle Valo .init_aggregation = rtl8723bu_init_aggregation,
1728028fa281SKalle Valo .init_statistics = rtl8723bu_init_statistics,
1729028fa281SKalle Valo .init_burst = rtl8xxxu_init_burst,
1730028fa281SKalle Valo .enable_rf = rtl8723b_enable_rf,
1731028fa281SKalle Valo .disable_rf = rtl8xxxu_gen2_disable_rf,
1732028fa281SKalle Valo .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1733028fa281SKalle Valo .set_tx_power = rtl8723b_set_tx_power,
1734028fa281SKalle Valo .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1735028fa281SKalle Valo .report_connect = rtl8xxxu_gen2_report_connect,
1736028fa281SKalle Valo .report_rssi = rtl8xxxu_gen2_report_rssi,
1737028fa281SKalle Valo .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1738028fa281SKalle Valo .set_crystal_cap = rtl8723a_set_crystal_cap,
1739028fa281SKalle Valo .cck_rssi = rtl8723b_cck_rssi,
1740028fa281SKalle Valo .led_classdev_brightness_set = rtl8723bu_led_brightness_set,
1741028fa281SKalle Valo .writeN_block_size = 1024,
1742028fa281SKalle Valo .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1743028fa281SKalle Valo .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1744028fa281SKalle Valo .has_s0s1 = 1,
1745028fa281SKalle Valo .has_tx_report = 1,
1746028fa281SKalle Valo .gen2_thermal_meter = 1,
1747028fa281SKalle Valo .needs_full_init = 1,
1748028fa281SKalle Valo .init_reg_hmtfr = 1,
1749028fa281SKalle Valo .ampdu_max_time = 0x5e,
1750028fa281SKalle Valo .ustime_tsf_edca = 0x50,
1751028fa281SKalle Valo .max_aggr_num = 0x0c14,
1752028fa281SKalle Valo .supports_ap = 1,
1753028fa281SKalle Valo .max_macid_num = 128,
1754028fa281SKalle Valo .max_sec_cam_num = 64,
1755028fa281SKalle Valo .adda_1t_init = 0x01c00014,
1756028fa281SKalle Valo .adda_1t_path_on = 0x01c00014,
1757028fa281SKalle Valo .adda_2t_path_on_a = 0x01c00014,
1758028fa281SKalle Valo .adda_2t_path_on_b = 0x01c00014,
1759028fa281SKalle Valo .trxff_boundary = 0x3f7f,
1760028fa281SKalle Valo .pbp_rx = PBP_PAGE_SIZE_256,
1761028fa281SKalle Valo .pbp_tx = PBP_PAGE_SIZE_256,
1762028fa281SKalle Valo .mactable = rtl8723b_mac_init_table,
1763028fa281SKalle Valo .total_page_num = TX_TOTAL_PAGE_NUM_8723B,
1764028fa281SKalle Valo .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B,
1765028fa281SKalle Valo .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B,
1766028fa281SKalle Valo .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B,
1767028fa281SKalle Valo };
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