Lines Matching +full:efuse +full:- +full:settings
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
5 #include "../efuse.h"
29 rtlpci->reg_bcn_ctrl_val |= set_bits; in _rtl92ee_set_bcn_ctrl_reg()
30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; in _rtl92ee_set_bcn_ctrl_reg()
32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); in _rtl92ee_set_bcn_ctrl_reg()
80 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, in _rtl92ee_set_fw_clock_on()
83 if (!rtlhal->fw_ready) in _rtl92ee_set_fw_clock_on()
85 if (!rtlpriv->psc.fw_current_inpsmode) in _rtl92ee_set_fw_clock_on()
89 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
90 if (rtlhal->fw_clk_change_in_progress) { in _rtl92ee_set_fw_clock_on()
91 while (rtlhal->fw_clk_change_in_progress) { in _rtl92ee_set_fw_clock_on()
92 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
97 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
99 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
101 rtlhal->fw_clk_change_in_progress = false; in _rtl92ee_set_fw_clock_on()
102 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
107 if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) { in _rtl92ee_set_fw_clock_on()
108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, in _rtl92ee_set_fw_clock_on()
121 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E; in _rtl92ee_set_fw_clock_on()
124 rtlhal->fw_ps_state); in _rtl92ee_set_fw_clock_on()
128 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
129 rtlhal->fw_clk_change_in_progress = false; in _rtl92ee_set_fw_clock_on()
130 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
132 mod_timer(&rtlpriv->works.fw_clockoff_timer, in _rtl92ee_set_fw_clock_on()
136 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
137 rtlhal->fw_clk_change_in_progress = false; in _rtl92ee_set_fw_clock_on()
138 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
152 if (!rtlhal->fw_ready) in _rtl92ee_set_fw_clock_off()
154 if (!rtlpriv->psc.fw_current_inpsmode) in _rtl92ee_set_fw_clock_off()
156 if (!rtlhal->allow_sw_to_change_hwclc) in _rtl92ee_set_fw_clock_off()
159 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); in _rtl92ee_set_fw_clock_off()
160 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) in _rtl92ee_set_fw_clock_off()
164 ring = &rtlpci->tx_ring[queue]; in _rtl92ee_set_fw_clock_off()
165 if (skb_queue_len(&ring->queue)) { in _rtl92ee_set_fw_clock_off()
172 mod_timer(&rtlpriv->works.fw_clockoff_timer, in _rtl92ee_set_fw_clock_off()
177 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) { in _rtl92ee_set_fw_clock_off()
178 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
179 if (!rtlhal->fw_clk_change_in_progress) { in _rtl92ee_set_fw_clock_off()
180 rtlhal->fw_clk_change_in_progress = true; in _rtl92ee_set_fw_clock_off()
181 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
182 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); in _rtl92ee_set_fw_clock_off()
184 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, in _rtl92ee_set_fw_clock_off()
186 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
187 rtlhal->fw_clk_change_in_progress = false; in _rtl92ee_set_fw_clock_off()
188 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
190 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
191 mod_timer(&rtlpriv->works.fw_clockoff_timer, in _rtl92ee_set_fw_clock_off()
228 if (ppsc->low_power_enable) { in _rtl92ee_fwlps_leave()
231 rtlhal->allow_sw_to_change_hwclc = false; in _rtl92ee_fwlps_leave()
232 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in _rtl92ee_fwlps_leave()
234 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, in _rtl92ee_fwlps_leave()
238 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, in _rtl92ee_fwlps_leave()
240 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in _rtl92ee_fwlps_leave()
242 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, in _rtl92ee_fwlps_leave()
255 if (ppsc->low_power_enable) { in _rtl92ee_fwlps_enter()
257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, in _rtl92ee_fwlps_enter()
259 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in _rtl92ee_fwlps_enter()
260 (u8 *)(&ppsc->fwctrl_psmode)); in _rtl92ee_fwlps_enter()
261 rtlhal->allow_sw_to_change_hwclc = true; in _rtl92ee_fwlps_enter()
265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, in _rtl92ee_fwlps_enter()
267 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in _rtl92ee_fwlps_enter()
268 (u8 *)(&ppsc->fwctrl_psmode)); in _rtl92ee_fwlps_enter()
269 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, in _rtl92ee_fwlps_enter()
282 *((u32 *)(val)) = rtlpci->receive_config; in rtl92ee_get_hw_reg()
285 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92ee_get_hw_reg()
291 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, in rtl92ee_get_hw_reg()
306 *((bool *)(val)) = ppsc->fw_current_inpsmode; in rtl92ee_get_hw_reg()
412 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw)); in rtl92ee_set_hw_reg() local
441 if (!mac->ht_enable) in rtl92ee_set_hw_reg()
456 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, in rtl92ee_set_hw_reg()
464 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5; in rtl92ee_set_hw_reg()
468 rtlpriv->mac80211.short_preamble = short_preamble; in rtl92ee_set_hw_reg()
505 if (rtlpci->acm_method != EACMWAY2_SW) in rtl92ee_set_hw_reg()
506 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, in rtl92ee_set_hw_reg()
512 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs); in rtl92ee_set_hw_reg()
514 u8 acm = aifs->f.acm; in rtl92ee_set_hw_reg()
517 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); in rtl92ee_set_hw_reg()
563 rtlpci->receive_config = ((u32 *)(val))[0]; in rtl92ee_set_hw_reg()
578 efuse->efuse_usedbytes = *((u16 *)val); in rtl92ee_set_hw_reg()
581 efuse->efuse_usedpercentage = *((u8 *)val); in rtl92ee_set_hw_reg()
604 ppsc->fw_current_inpsmode = *((bool *)val); in rtl92ee_set_hw_reg()
622 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); in rtl92ee_set_hw_reg()
637 (u2btmp | mac->assoc_id)); in rtl92ee_set_hw_reg()
649 (u32)(mac->tsf & 0xffffffff)); in rtl92ee_set_hw_reg()
651 (u32)((mac->tsf >> 32) & 0xffffffff)); in rtl92ee_set_hw_reg()
685 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1); in _rtl92ee_llt_table_init()
717 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; in _rtl92ee_gen_refresh_led_state()
719 if (rtlpriv->rtlhal.up_first_time) in _rtl92ee_gen_refresh_led_state()
722 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) in _rtl92ee_gen_refresh_led_state()
724 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) in _rtl92ee_gen_refresh_led_state()
796 if (!rtlhal->mac_func_enable) { in _rtl92ee_init_mac()
815 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); in _rtl92ee_init_mac()
819 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); in _rtl92ee_init_mac()
821 /* Set TX/RX descriptor physical address -- HI part */ in _rtl92ee_init_mac()
822 if (!rtlpriv->cfg->mod_params->dma64) in _rtl92ee_init_mac()
826 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) >> in _rtl92ee_init_mac()
829 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma >> 32); in _rtl92ee_init_mac()
831 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma >> 32); in _rtl92ee_init_mac()
833 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma >> 32); in _rtl92ee_init_mac()
835 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma >> 32); in _rtl92ee_init_mac()
837 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma >> 32); in _rtl92ee_init_mac()
839 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma >> 32); in _rtl92ee_init_mac()
842 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma >> 32); in _rtl92ee_init_mac()
848 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) & in _rtl92ee_init_mac()
851 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma & in _rtl92ee_init_mac()
854 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma & in _rtl92ee_init_mac()
857 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma & in _rtl92ee_init_mac()
861 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma & in _rtl92ee_init_mac()
867 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma & in _rtl92ee_init_mac()
870 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma & in _rtl92ee_init_mac()
874 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma & in _rtl92ee_init_mac()
950 /* CF-End setting. */ in _rtl92ee_hw_configure()
956 /* BAR settings */ in _rtl92ee_hw_configure()
969 rtlpci->reg_bcn_ctrl_val = 0x1d; in _rtl92ee_hw_configure()
970 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); in _rtl92ee_hw_configure()
972 /* Marked out by Bruce, 2010-09-09. in _rtl92ee_hw_configure()
1088 if (ppsc->support_backdoor || (0 == tmp8)) { in _rtl92ee_enable_aspm_back_door()
1112 rtlpriv->sec.pairwise_enc_algorithm, in rtl92ee_enable_hw_security_config()
1113 rtlpriv->sec.group_enc_algorithm); in rtl92ee_enable_hw_security_config()
1115 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { in rtl92ee_enable_hw_security_config()
1123 if (rtlpriv->sec.use_defaultkey) { in rtl92ee_enable_hw_security_config()
1134 "The SECR-value %x\n", sec_reg_value); in rtl92ee_enable_hw_security_config()
1136 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); in rtl92ee_enable_hw_security_config()
1277 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_hw_init()
1285 rtlpriv->rtlhal.being_init_adapter = true; in rtl92ee_hw_init()
1286 rtlpriv->intf_ops->disable_aspm(hw); in rtl92ee_hw_init()
1291 rtlhal->mac_func_enable = true; in rtl92ee_hw_init()
1293 rtlhal->mac_func_enable = false; in rtl92ee_hw_init()
1294 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E; in rtl92ee_hw_init()
1300 rtlhal->mac_func_enable); in rtl92ee_hw_init()
1301 rtlhal->mac_func_enable = false; in rtl92ee_hw_init()
1314 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) { in rtl92ee_hw_init()
1329 rtlhal->fw_ready = false; in rtl92ee_hw_init()
1332 rtlhal->fw_ready = true; in rtl92ee_hw_init()
1334 ppsc->fw_current_inpsmode = false; in rtl92ee_hw_init()
1335 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E; in rtl92ee_hw_init()
1336 rtlhal->fw_clk_change_in_progress = false; in rtl92ee_hw_init()
1337 rtlhal->allow_sw_to_change_hwclc = false; in rtl92ee_hw_init()
1338 rtlhal->last_hmeboxnum = 0; in rtl92ee_hw_init()
1346 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A, in rtl92ee_hw_init()
1348 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B, in rtl92ee_hw_init()
1350 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1, in rtl92ee_hw_init()
1352 rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) | in rtl92ee_hw_init()
1356 rtlphy->rfreg_chnlval[0]); in rtl92ee_hw_init()
1358 rtlphy->rfreg_chnlval[0]); in rtl92ee_hw_init()
1360 /*---- Set CCK and OFDM Block "ON"----*/ in rtl92ee_hw_init()
1372 rtlhal->mac_func_enable = true; in rtl92ee_hw_init()
1377 ppsc->rfpwr_state = ERFON; in rtl92ee_hw_init()
1379 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); in rtl92ee_hw_init()
1381 rtlpriv->intf_ops->enable_aspm(hw); in rtl92ee_hw_init()
1385 rtlpriv->rtlhal.being_init_adapter = false; in rtl92ee_hw_init()
1387 if (ppsc->rfpwr_state == ERFON) { in rtl92ee_hw_init()
1388 if (rtlphy->iqk_initialized) { in rtl92ee_hw_init()
1392 rtlphy->iqk_initialized = true; in rtl92ee_hw_init()
1396 rtlphy->rfpath_rx_enable[0] = true; in rtl92ee_hw_init()
1397 if (rtlphy->rf_type == RF_2T2R) in rtl92ee_hw_init()
1398 rtlphy->rfpath_rx_enable[1] = true; in rtl92ee_hw_init()
1406 if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) { in rtl92ee_hw_init()
1431 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_read_chip_version()
1435 rtlphy->rf_type = RF_2T2R; in _rtl92ee_read_chip_version()
1444 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ? in _rtl92ee_read_chip_version()
1493 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) { in _rtl92ee_set_media_status()
1511 rtlpriv->cfg->ops->led_control(hw, ledaction); in _rtl92ee_set_media_status()
1523 u32 reg_rcr = rtlpci->receive_config; in rtl92ee_set_check_bssid()
1525 if (rtlpriv->psc.rfpwr_state != ERFON) in rtl92ee_set_check_bssid()
1530 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, in rtl92ee_set_check_bssid()
1536 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, in rtl92ee_set_check_bssid()
1546 return -EOPNOTSUPP; in rtl92ee_set_network_type()
1548 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { in rtl92ee_set_network_type()
1589 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92ee_enable_interrupt()
1590 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92ee_enable_interrupt()
1591 rtlpci->irq_enabled = true; in rtl92ee_enable_interrupt()
1601 rtlpci->irq_enabled = false; in rtl92ee_disable_interrupt()
1602 /*synchronize_irq(rtlpci->pdev->irq);*/ in rtl92ee_disable_interrupt()
1611 rtlhal->mac_func_enable = false; in _rtl92ee_poweroff_adapter()
1622 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) in _rtl92ee_poweroff_adapter()
1657 mac->link_state = MAC80211_NOLINK; in rtl92ee_card_disable()
1662 if (rtlpriv->rtlhal.driver_is_goingto_unload || in rtl92ee_card_disable()
1663 ppsc->rfoff_reason > RF_CHANGE_BY_PS) in rtl92ee_card_disable()
1664 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); in rtl92ee_card_disable()
1669 if (!rtlpriv->cfg->ops->get_btc_status()) in rtl92ee_card_disable()
1670 rtlpriv->phy.iqk_initialized = false; in rtl92ee_card_disable()
1679 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92ee_interrupt_recognized()
1680 rtl_write_dword(rtlpriv, ISR, intvec->inta); in rtl92ee_interrupt_recognized()
1682 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; in rtl92ee_interrupt_recognized()
1683 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb); in rtl92ee_interrupt_recognized()
1693 bcn_interval = mac->beacon_interval; in rtl92ee_set_beacon_related_registers()
1702 rtlpci->reg_bcn_ctrl_val |= BIT(3); in rtl92ee_set_beacon_related_registers()
1703 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); in rtl92ee_set_beacon_related_registers()
1710 u16 bcn_interval = mac->beacon_interval; in rtl92ee_set_beacon_interval()
1727 rtlpci->irq_mask[0] |= add_msr; in rtl92ee_update_interrupt_mask()
1729 rtlpci->irq_mask[0] &= (~rm_msr); in rtl92ee_update_interrupt_mask()
1802 pwr2g->index_cck_base[rf][group] = 0x2D; in _rtl8192ee_read_power_value_fromprom()
1803 pwr2g->index_bw40_base[rf][group] = 0x2D; in _rtl8192ee_read_power_value_fromprom()
1807 pwr2g->bw20_diff[rf][0] = 0x02; in _rtl8192ee_read_power_value_fromprom()
1808 pwr2g->ofdm_diff[rf][0] = 0x04; in _rtl8192ee_read_power_value_fromprom()
1810 pwr2g->bw20_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1811 pwr2g->bw40_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1812 pwr2g->cck_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1813 pwr2g->ofdm_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1819 pwr5g->index_bw40_base[rf][group] = 0x2A; in _rtl8192ee_read_power_value_fromprom()
1823 pwr5g->ofdm_diff[rf][0] = 0x04; in _rtl8192ee_read_power_value_fromprom()
1824 pwr5g->bw20_diff[rf][0] = 0x00; in _rtl8192ee_read_power_value_fromprom()
1825 pwr5g->bw80_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1826 pwr5g->bw160_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1828 pwr5g->ofdm_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1829 pwr5g->bw20_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1830 pwr5g->bw40_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1831 pwr5g->bw80_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1832 pwr5g->bw160_diff[rf][0] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1839 rtl_priv(hw)->efuse.txpwr_fromeprom = true; in _rtl8192ee_read_power_value_fromprom()
1844 pwr2g->index_cck_base[rf][group] = hwinfo[addr++]; in _rtl8192ee_read_power_value_fromprom()
1845 if (pwr2g->index_cck_base[rf][group] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1846 pwr2g->index_cck_base[rf][group] = 0x2D; in _rtl8192ee_read_power_value_fromprom()
1848 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { in _rtl8192ee_read_power_value_fromprom()
1849 pwr2g->index_bw40_base[rf][group] = hwinfo[addr++]; in _rtl8192ee_read_power_value_fromprom()
1850 if (pwr2g->index_bw40_base[rf][group] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1851 pwr2g->index_bw40_base[rf][group] = 0x2D; in _rtl8192ee_read_power_value_fromprom()
1855 pwr2g->bw40_diff[rf][i] = 0; in _rtl8192ee_read_power_value_fromprom()
1857 pwr2g->bw20_diff[rf][i] = 0x02; in _rtl8192ee_read_power_value_fromprom()
1859 pwr2g->bw20_diff[rf][i] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1861 if (pwr2g->bw20_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1862 pwr2g->bw20_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1866 pwr2g->ofdm_diff[rf][i] = 0x04; in _rtl8192ee_read_power_value_fromprom()
1868 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1870 if (pwr2g->ofdm_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1871 pwr2g->ofdm_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1873 pwr2g->cck_diff[rf][i] = 0; in _rtl8192ee_read_power_value_fromprom()
1877 pwr2g->bw40_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1879 pwr2g->bw40_diff[rf][i] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1881 if (pwr2g->bw40_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1882 pwr2g->bw40_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1886 pwr2g->bw20_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1888 pwr2g->bw20_diff[rf][i] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1890 if (pwr2g->bw20_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1891 pwr2g->bw20_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1896 pwr2g->ofdm_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1898 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1900 if (pwr2g->ofdm_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1901 pwr2g->ofdm_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1905 pwr2g->cck_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1907 pwr2g->cck_diff[rf][i] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1909 if (pwr2g->cck_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1910 pwr2g->cck_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1918 pwr5g->index_bw40_base[rf][group] = hwinfo[addr++]; in _rtl8192ee_read_power_value_fromprom()
1919 if (pwr5g->index_bw40_base[rf][group] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1920 pwr5g->index_bw40_base[rf][group] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1925 pwr5g->bw40_diff[rf][i] = 0; in _rtl8192ee_read_power_value_fromprom()
1928 pwr5g->bw20_diff[rf][i] = 0; in _rtl8192ee_read_power_value_fromprom()
1930 pwr5g->bw20_diff[rf][0] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1932 if (pwr5g->bw20_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1933 pwr5g->bw20_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1937 pwr5g->ofdm_diff[rf][i] = 0x04; in _rtl8192ee_read_power_value_fromprom()
1939 pwr5g->ofdm_diff[rf][0] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1941 if (pwr5g->ofdm_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1942 pwr5g->ofdm_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1947 pwr5g->bw40_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1949 pwr5g->bw40_diff[rf][i] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1951 if (pwr5g->bw40_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1952 pwr5g->bw40_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1956 pwr5g->bw20_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1958 pwr5g->bw20_diff[rf][i] = (hwinfo[addr] in _rtl8192ee_read_power_value_fromprom()
1960 if (pwr5g->bw20_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1961 pwr5g->bw20_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1968 pwr5g->ofdm_diff[rf][1] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1969 pwr5g->ofdm_diff[rf][2] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1971 pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4; in _rtl8192ee_read_power_value_fromprom()
1972 pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1977 pwr5g->ofdm_diff[rf][3] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1979 pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f); in _rtl8192ee_read_power_value_fromprom()
1983 if (pwr5g->ofdm_diff[rf][i] == 0xFF) in _rtl8192ee_read_power_value_fromprom()
1984 pwr5g->ofdm_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1985 else if (pwr5g->ofdm_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1986 pwr5g->ofdm_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
1991 pwr5g->bw80_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
1993 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0) in _rtl8192ee_read_power_value_fromprom()
1995 if (pwr5g->bw80_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
1996 pwr5g->bw80_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
2000 pwr5g->bw160_diff[rf][i] = 0xFE; in _rtl8192ee_read_power_value_fromprom()
2002 pwr5g->bw160_diff[rf][i] = in _rtl8192ee_read_power_value_fromprom()
2004 if (pwr5g->bw160_diff[rf][i] & BIT(3)) in _rtl8192ee_read_power_value_fromprom()
2005 pwr5g->bw160_diff[rf][i] |= 0xF0; in _rtl8192ee_read_power_value_fromprom()
2029 if (i == CHANNEL_MAX_NUMBER_2G - 1) { in _rtl92ee_read_txpower_info_from_hwpg()
2030 efu->txpwrlevel_cck[rf][i] = in _rtl92ee_read_txpower_info_from_hwpg()
2032 efu->txpwrlevel_ht40_1s[rf][i] = in _rtl92ee_read_txpower_info_from_hwpg()
2035 efu->txpwrlevel_cck[rf][i] = in _rtl92ee_read_txpower_info_from_hwpg()
2037 efu->txpwrlevel_ht40_1s[rf][i] = in _rtl92ee_read_txpower_info_from_hwpg()
2043 efu->txpwr_5g_bw40base[rf][i] = in _rtl92ee_read_txpower_info_from_hwpg()
2053 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2; in _rtl92ee_read_txpower_info_from_hwpg()
2056 efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i]; in _rtl92ee_read_txpower_info_from_hwpg()
2057 efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i]; in _rtl92ee_read_txpower_info_from_hwpg()
2058 efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i]; in _rtl92ee_read_txpower_info_from_hwpg()
2059 efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i]; in _rtl92ee_read_txpower_info_from_hwpg()
2061 efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i]; in _rtl92ee_read_txpower_info_from_hwpg()
2062 efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i]; in _rtl92ee_read_txpower_info_from_hwpg()
2063 efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i]; in _rtl92ee_read_txpower_info_from_hwpg()
2064 efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i]; in _rtl92ee_read_txpower_info_from_hwpg()
2069 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E]; in _rtl92ee_read_txpower_info_from_hwpg()
2071 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; in _rtl92ee_read_txpower_info_from_hwpg()
2073 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) { in _rtl92ee_read_txpower_info_from_hwpg()
2074 efu->apk_thermalmeterignore = true; in _rtl92ee_read_txpower_info_from_hwpg()
2075 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; in _rtl92ee_read_txpower_info_from_hwpg()
2078 efu->thermalmeter[0] = efu->eeprom_thermalmeter; in _rtl92ee_read_txpower_info_from_hwpg()
2080 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter); in _rtl92ee_read_txpower_info_from_hwpg()
2083 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E] in _rtl92ee_read_txpower_info_from_hwpg()
2086 efu->eeprom_regulatory = 0; in _rtl92ee_read_txpower_info_from_hwpg()
2088 efu->eeprom_regulatory = 0; in _rtl92ee_read_txpower_info_from_hwpg()
2091 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory); in _rtl92ee_read_txpower_info_from_hwpg()
2112 if (rtlefuse->eeprom_oemid == 0xFF) in _rtl92ee_read_adapter_info()
2113 rtlefuse->eeprom_oemid = 0; in _rtl92ee_read_adapter_info()
2116 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); in _rtl92ee_read_adapter_info()
2117 /* set channel plan from efuse */ in _rtl92ee_read_adapter_info()
2118 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; in _rtl92ee_read_adapter_info()
2120 _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, in _rtl92ee_read_adapter_info()
2123 rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag, in _rtl92ee_read_adapter_info()
2127 rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) in _rtl92ee_read_adapter_info()
2130 rtlefuse->board_type = 0; in _rtl92ee_read_adapter_info()
2132 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) in _rtl92ee_read_adapter_info()
2133 rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */ in _rtl92ee_read_adapter_info()
2135 rtlhal->board_type = rtlefuse->board_type; in _rtl92ee_read_adapter_info()
2137 "board_type = 0x%x\n", rtlefuse->board_type); in _rtl92ee_read_adapter_info()
2139 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E]; in _rtl92ee_read_adapter_info()
2141 rtlefuse->crystalcap = 0x20; in _rtl92ee_read_adapter_info()
2144 rtlefuse->antenna_div_type = NO_ANTDIV; in _rtl92ee_read_adapter_info()
2145 rtlefuse->antenna_div_cfg = 0; in _rtl92ee_read_adapter_info()
2147 if (rtlhal->oem_id == RT_CID_DEFAULT) { in _rtl92ee_read_adapter_info()
2148 switch (rtlefuse->eeprom_oemid) { in _rtl92ee_read_adapter_info()
2150 if (rtlefuse->eeprom_did == 0x818B) { in _rtl92ee_read_adapter_info()
2151 if ((rtlefuse->eeprom_svid == 0x10EC) && in _rtl92ee_read_adapter_info()
2152 (rtlefuse->eeprom_smid == 0x001B)) in _rtl92ee_read_adapter_info()
2153 rtlhal->oem_id = RT_CID_819X_LENOVO; in _rtl92ee_read_adapter_info()
2155 rtlhal->oem_id = RT_CID_DEFAULT; in _rtl92ee_read_adapter_info()
2159 rtlhal->oem_id = RT_CID_DEFAULT; in _rtl92ee_read_adapter_info()
2172 rtlpriv->ledctl.led_opendrain = true; in _rtl92ee_hal_customized_behavior()
2175 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); in _rtl92ee_hal_customized_behavior()
2182 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_read_eeprom_info()
2186 rtlhal->version = _rtl92ee_read_chip_version(hw); in rtl92ee_read_eeprom_info()
2188 rtlpriv->dm.rfpath_rxenable[0] = true; in rtl92ee_read_eeprom_info()
2190 rtlpriv->dm.rfpath_rxenable[0] = true; in rtl92ee_read_eeprom_info()
2191 rtlpriv->dm.rfpath_rxenable[1] = true; in rtl92ee_read_eeprom_info()
2194 rtlhal->version); in rtl92ee_read_eeprom_info()
2198 rtlefuse->epromtype = EEPROM_93C46; in rtl92ee_read_eeprom_info()
2200 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); in rtl92ee_read_eeprom_info()
2201 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; in rtl92ee_read_eeprom_info()
2205 rtlefuse->autoload_failflag = false; in rtl92ee_read_eeprom_info()
2212 rtlphy->rfpath_rx_enable[0] = true; in rtl92ee_read_eeprom_info()
2213 if (rtlphy->rf_type == RF_2T2R) in rtl92ee_read_eeprom_info()
2214 rtlphy->rfpath_rx_enable[1] = true; in rtl92ee_read_eeprom_info()
2253 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_update_hal_rate_mask()
2258 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) in rtl92ee_update_hal_rate_mask()
2260 u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? in rtl92ee_update_hal_rate_mask()
2262 u8 b_curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? in rtl92ee_update_hal_rate_mask()
2269 sta_entry = (struct rtl_sta_info *)sta->drv_priv; in rtl92ee_update_hal_rate_mask()
2270 wirelessmode = sta_entry->wireless_mode; in rtl92ee_update_hal_rate_mask()
2271 if (mac->opmode == NL80211_IFTYPE_STATION || in rtl92ee_update_hal_rate_mask()
2272 mac->opmode == NL80211_IFTYPE_MESH_POINT) in rtl92ee_update_hal_rate_mask()
2273 curtxbw_40mhz = mac->bw_40; in rtl92ee_update_hal_rate_mask()
2274 else if (mac->opmode == NL80211_IFTYPE_AP || in rtl92ee_update_hal_rate_mask()
2275 mac->opmode == NL80211_IFTYPE_ADHOC) in rtl92ee_update_hal_rate_mask()
2276 macid = sta->aid + 1; in rtl92ee_update_hal_rate_mask()
2278 ratr_bitmap = sta->deflink.supp_rates[0]; in rtl92ee_update_hal_rate_mask()
2279 if (mac->opmode == NL80211_IFTYPE_ADHOC) in rtl92ee_update_hal_rate_mask()
2282 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | in rtl92ee_update_hal_rate_mask()
2283 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92ee_update_hal_rate_mask()
2309 if (rtlphy->rf_type == RF_1T1R) { in rtl92ee_update_hal_rate_mask()
2354 if (rtlphy->rf_type == RF_1T1R) in rtl92ee_update_hal_rate_mask()
2361 sta_entry->ratr_index = ratr_index; in rtl92ee_update_hal_rate_mask()
2389 if (rtlpriv->dm.useramask) in rtl92ee_update_hal_rate_tbl()
2399 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, in rtl92ee_update_channel_access_setting()
2400 (u8 *)&mac->slot_time); in rtl92ee_update_channel_access_setting()
2401 if (!mac->ht_enable) in rtl92ee_update_channel_access_setting()
2405 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); in rtl92ee_update_channel_access_setting()
2447 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92ee_set_key()
2449 rtlpriv->sec.key_len[idx] = 0; in rtl92ee_set_key()
2474 if (is_wepkey || rtlpriv->sec.use_defaultkey) { in rtl92ee_set_key()
2482 if (mac->opmode == NL80211_IFTYPE_AP || in rtl92ee_set_key()
2483 mac->opmode == NL80211_IFTYPE_MESH_POINT) { in rtl92ee_set_key()
2499 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92ee_set_key()
2503 if (mac->opmode == NL80211_IFTYPE_AP || in rtl92ee_set_key()
2504 mac->opmode == NL80211_IFTYPE_MESH_POINT) in rtl92ee_set_key()
2517 rtlpriv->sec.key_buf[key_index]); in rtl92ee_set_key()
2522 if (mac->opmode == NL80211_IFTYPE_ADHOC) { in rtl92ee_set_key()
2524 rtlefuse->dev_addr, in rtl92ee_set_key()
2528 rtlpriv->sec.key_buf[entry_id]); in rtl92ee_set_key()
2534 rtlpriv->sec.key_buf[entry_id]); in rtl92ee_set_key()
2549 rtlpriv->btcoexist.btc_info.btcoexist = 1; in rtl92ee_read_bt_coexist_info_from_hwpg()
2551 rtlpriv->btcoexist.btc_info.btcoexist = 0; in rtl92ee_read_bt_coexist_info_from_hwpg()
2553 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E; in rtl92ee_read_bt_coexist_info_from_hwpg()
2554 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; in rtl92ee_read_bt_coexist_info_from_hwpg()
2556 rtlpriv->btcoexist.btc_info.btcoexist = 1; in rtl92ee_read_bt_coexist_info_from_hwpg()
2557 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E; in rtl92ee_read_bt_coexist_info_from_hwpg()
2558 rtlpriv->btcoexist.btc_info.ant_num = ANT_X1; in rtl92ee_read_bt_coexist_info_from_hwpg()
2566 /* 0:Low, 1:High, 2:From Efuse. */ in rtl92ee_bt_reg_init()
2567 rtlpriv->btcoexist.reg_bt_iso = 2; in rtl92ee_bt_reg_init()
2568 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ in rtl92ee_bt_reg_init()
2569 rtlpriv->btcoexist.reg_bt_sco = 3; in rtl92ee_bt_reg_init()
2570 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ in rtl92ee_bt_reg_init()
2571 rtlpriv->btcoexist.reg_bt_sco = 0; in rtl92ee_bt_reg_init()
2578 if (rtlpriv->cfg->ops->get_btc_status()) in rtl92ee_bt_hw_init()
2579 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); in rtl92ee_bt_hw_init()
2598 rtlpci->receive_config |= RCR_AAP; in rtl92ee_allow_all_destaddr()
2600 rtlpci->receive_config &= ~RCR_AAP; in rtl92ee_allow_all_destaddr()
2603 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); in rtl92ee_allow_all_destaddr()
2607 rtlpci->receive_config, write_into_reg); in rtl92ee_allow_all_destaddr()