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/linux/Documentation/devicetree/bindings/display/msm/
H A Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp
[all …]
H A Dqcom,sc7280-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
[all …]
H A Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <quic_jhugo@quicinc.com>
11 - Taniya Das <quic_tdas@quicinc.com>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
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H A Dqcom,sc7280-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
16 See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
20 const: qcom,sc7280-dispcc
24 - description: Board XO source
25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY
[all …]
H A Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
[all …]
/linux/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
38 Enable this to support the Rockchip Innosilicon HDMI PHY.
49 Support for Rockchip USB2.0 PHY with Innosilicon IP block.
[all …]
H A Dphy-rockchip-dp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip DP PHY driver
6 * Author: Yakir Yang <ykk@@rock-chips.com>
13 #include <linux/phy/phy.h>
32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument
34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state()
38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state()
42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state()
46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state()
48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp-crd.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sc8280xp-pmics.dtsi"
17 compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp";
26 compatible = "pwm-backlight";
28 enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>;
29 power-supply = <&vreg_edp_bl>;
31 pinctrl-names = "default";
[all …]
H A Dsc7280-qcard.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if
14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
16 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
34 wcd9385: audio-codec-1 {
35 compatible = "qcom,wcd9385-codec";
36 pinctrl-names = "default", "sleep";
37 pinctrl-0 = <&wcd_reset_n>, <&us_euro_hs_sel>;
[all …]
H A Dsc8280xp-lenovo-thinkpad-x13s.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/gpio-keys.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
17 #include "sc8280xp-pmics.dtsi"
21 compatible = "lenovo,thinkpad-x13s", "qcom,sc8280xp";
[all …]
H A Dx1e80100-microsoft-romulus.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include "x1e80100-pmics.dtsi"
24 compatible = "pwm-backlight";
26 enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
27 /* TODO: power-supply? */
29 pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>;
30 pinctrl-names = "default";
[all …]
H A Dx1e80100-asus-vivobook-s15.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "x1e80100-pmics.dtsi"
17 compatible = "asus,vivobook-s15", "qcom,x1e80100";
18 chassis-type = "laptop";
20 pmic-glink {
21 compatible = "qcom,x1e80100-pmic-glink",
22 "qcom,sm8550-pmic-glink",
[all …]
H A Dx1e78100-lenovo-thinkpad-t14s.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
15 #include "x1e80100-pmics.dtsi"
19 compatible = "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100";
20 chassis-type = "laptop";
22 gpio-keys {
[all …]
/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
5 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
6 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
7 obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
8 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
10 obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o
11 obj-$(CONFIG_PHY_QCOM_QMP_PCIE) += phy-qcom-qmp-pcie.o
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,rk3288-dp-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Analogix Display Port PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3288-dp-phy
19 clock-names:
22 "#phy-cells":
26 - compatible
[all …]
H A Drockchip,rk3588-hdptx-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
10 - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
15 - rockchip,rk3588-hdptx-phy
22 - description: Reference clock
23 - description: APB clock
25 clock-names:
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_alpm.c1 // SPDX-License-Identifier: MIT
16 return intel_dp->alpm_dpcd & DP_ALPM_CAP; in intel_alpm_aux_wake_supported()
21 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP; in intel_alpm_aux_less_wake_supported()
28 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) in intel_alpm_init_dpcd()
31 intel_dp->alpm_dpcd = dpcd; in intel_alpm_init_dpcd()
37 * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2)
41 * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns
44 * Link rates 5.4 - 8.1
46 * LFPS Period chosen is the mid-point of the min:max values from the table
96 *silence_period = *lfps_half_cycle = -1; in _lnl_get_silence_period_and_lfps_half_cycle()
[all …]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c66 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
93 return -EFAULT; in parse_write_buffer_into_params()
107 /* skip non-space*/ in parse_write_buffer_into_params()
156 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
158 * --- to get dp configuration
160 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
163 * current -- for current video mode
164 * verified --- maximum configuration which pass link training
165 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
166 * preferred --- user force settings
[all …]
/linux/drivers/gpu/drm/amd/display/include/
H A Dlink_service_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 /* eDP version 1.1 or lower */
45 /* eDP version 1.2 */
47 /* eDP version 1.3 */
99 * training states - parameters that can change in link training
105 * a constant input pre-decided prior to link training.
123 /* phy test patterns*/
190 /* standard mode for eDP */
/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
20 - $ref: /schemas/display/dsi-controller.yaml#
25 - enum:
26 - mediatek,mt2701-dsi
[all …]
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
12 #include <linux/phy/phy.h>
32 MODULE_PARM_DESC(psr_enabled, "enable PSR for eDP and DP displays");
165 { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_descs },
166 { .compatible = "qcom,sc7280-dp", .data = &sc7280_dp_descs },
167 { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_descs },
168 { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_descs },
169 { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_descs },
170 { .compatible = "qcom,sc8280xp-dp", .data = &sc8280xp_dp_descs },
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Danalogix,dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
21 clock-names: true
25 phy-names:
28 force-hpd:
32 is used for some eDP screen which don not have a hpd signal.
34 hpd-gpios:
51 Port node with one endpoint connected to a dp-connector node.
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include "rk3399-base.dtsi"
12 compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
20 compatible = "pwm-backlight";
21 brightness-levels = <
54 default-brightness-level = <200>;
58 edp_panel: edp-panel {
59 compatible = "lg,lp079qx1-sp0v";
[all …]

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