Lines Matching +full:edp +full:- +full:phy
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
33 - const: vbif_phys
34 - const: vbif_nrt_phys
39 interrupt-controller: true
41 "#interrupt-cells":
44 power-domains:
51 - minItems: 3
53 - description: Display abh clock
54 - description: Display axi clock
55 - description: Display vsync clock
56 - description: Display core clock
57 - minItems: 1
59 - description: Display abh clock
60 - description: Display core clock
62 clock-names:
64 - minItems: 3
66 - const: iface
67 - const: bus
68 - const: vsync
69 - const: core
70 - minItems: 1
72 - const: iface
73 - const: core
75 "#address-cells":
78 "#size-cells":
85 - description: MDSS_CORE reset
88 - compatible
89 - reg
90 - reg-names
91 - interrupts
92 - interrupt-controller
93 - "#interrupt-cells"
94 - power-domains
95 - clocks
96 - clock-names
97 - "#address-cells"
98 - "#size-cells"
99 - ranges
102 "^display-controller@[1-9a-f][0-9a-f]*$":
110 "^dsi@[1-9a-f][0-9a-f]*$":
116 const: qcom,mdss-dsi-ctrl
118 "^phy@[1-9a-f][0-9a-f]*$":
124 - qcom,dsi-phy-14nm
125 - qcom,dsi-phy-14nm-660
126 - qcom,dsi-phy-14nm-8953
127 - qcom,dsi-phy-20nm
128 - qcom,dsi-phy-28nm-8226
129 - qcom,dsi-phy-28nm-8937
130 - qcom,dsi-phy-28nm-hpm
131 - qcom,dsi-phy-28nm-hpm-fam-b
132 - qcom,dsi-phy-28nm-lp
133 - qcom,hdmi-phy-8084
134 - qcom,hdmi-phy-8660
135 - qcom,hdmi-phy-8960
136 - qcom,hdmi-phy-8974
137 - qcom,hdmi-phy-8996
139 "^hdmi-tx@[1-9a-f][0-9a-f]*$":
145 - qcom,hdmi-tx-8084
146 - qcom,hdmi-tx-8660
147 - qcom,hdmi-tx-8960
148 - qcom,hdmi-tx-8974
149 - qcom,hdmi-tx-8994
150 - qcom,hdmi-tx-8996
155 - |
156 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
157 #include <dt-bindings/interrupt-controller/arm-gic.h>
158 display-subsystem@1a00000 {
162 reg-names = "mdss_phys", "vbif_phys";
164 power-domains = <&gcc MDSS_GDSC>;
169 clock-names = "iface",
175 interrupt-controller;
176 #interrupt-cells = <1>;
178 #address-cells = <1>;
179 #size-cells = <1>;
182 display-controller@1a01000 {
183 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
185 reg-names = "mdp_phys";
187 interrupt-parent = <&mdss>;
194 clock-names = "iface",
202 #address-cells = <1>;
203 #size-cells = <0>;
208 remote-endpoint = <&dsi0_in>;