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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dthine,thc63lvd1024.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Thine Electronics THC63LVD1024 LVDS Decoder
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
15 streams to parallel data outputs. The chip supports single/dual input/output
16 modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
19 Single or dual operation mode, output data mapping and DDR output modes are
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H A Dlontium,lt9211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
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H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358775 DSI to LVDS bridge
10 - Vinay Simha BN <simhavcs@gmail.com>
13 This binding supports DSI to LVDS bridges TC358765 and TC358775
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
18 limited by 135 MHz LVDS speed
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
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H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
23 LDB split mode to support a dual link LVDS display. The channel indexes
29 in dual mode or split mode. In dual mode, the two channels output identical
41 - fsl,imx8qm-ldb
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H A Drenesas,lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car LVDS Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
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H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
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/linux/arch/arm64/boot/dts/renesas/
H A Dr8a774c0-ek874-idk-2121wr.dts1 // SPDX-License-Identifier: GPL-2.0
4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel
9 #include "r8a774c0-ek874.dts"
13 compatible = "pwm-backlight";
16 brightness-levels = <0 4 8 16 32 64 128 255>;
17 default-brightness-level = <6>;
19 power-supply = <&reg_12p0v>;
20 enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
23 panel-lvds {
24 compatible = "advantech,idk-2121wr", "panel-lvds";
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/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx6q-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale LVDS Display Bridge (ldb)
10 The LVDS Display Bridge device tree node contains up to two lvds-channel
11 nodes describing each of the two LVDS encoder channels of the bridge.
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,imx53-ldb
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-evk-mx8-dlvds-lcd1.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 panel-lvds {
13 power-supply = <&reg_vext_3v3>;
15 panel-timing {
16 clock-frequency = <148500000>;
19 hfront-porch = <130>;
20 hback-porch = <70>;
21 hsync-len = <30>;
22 vfront-porch = <5>;
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H A Dimx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
11 #include <dt-bindings/clock/imx8mp-clock.h>
14 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
26 #address-cells = <1>;
27 #size-cells = <0>;
31 dual-lvds-odd-pixels;
34 remote-endpoint = <&ldb_lvds_ch0>;
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H A Dimx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtso1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
9 #include "imx8mp-pinfunc.h"
11 /dts-v1/;
15 model = "GOcontroll Moduline Display with BOE av123z7m-n17 display";
18 compatible = "boe,av123z7m-n17";
19 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
20 pinctrl-0 = <&pinctrl_panel>;
21 pinctrl-names = "default";
22 power-supply = <&reg_3v3_per>;
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/linux/Documentation/devicetree/bindings/display/
H A Dst,stm32mp25-lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 LVDS Display Interface Transmitter
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
16 onto the LVDS PHY.
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds_regs.h1 /* SPDX-License-Identifier: MIT */
11 /* LVDS port control */
12 #define LVDS _MMIO(0x61180) macro
14 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
15 * the DPLL semantics change when the LVDS is assigned to that pipe.
18 /* Selects pipe B for LVDS data. Must be set on pre-965. */
23 /* LVDS dithering flag on 965/g4x platform */
25 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
29 /* Enable border for unscaled (or aspect-scaled) display */
32 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
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/linux/include/linux/phy/
H A Dphy-lvds.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
13 * @differential_clk_rate: Clock rate, in Hertz, of the LVDS
20 * phy to support dual link transmission,
23 * This structure is used to represent the configuration state of a LVDS phy.
/linux/drivers/video/fbdev/via/
H A Dlcd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
7 #include <linux/via-core.h>
75 viaparinfo->lvds_setting_info2->lcd_panel_hres = in viafb_init_lcd_size()
76 viaparinfo->lvds_setting_info->lcd_panel_hres; in viafb_init_lcd_size()
77 viaparinfo->lvds_setting_info2->lcd_panel_vres = in viafb_init_lcd_size()
78 viaparinfo->lvds_setting_info->lcd_panel_vres; in viafb_init_lcd_size()
79 viaparinfo->lvds_setting_info2->device_lcd_dualedge = in viafb_init_lcd_size()
80 viaparinfo->lvds_setting_info->device_lcd_dualedge; in viafb_init_lcd_size()
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/linux/drivers/gpu/drm/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
109 bool "Rockchip LVDS support"
115 Choose this option to enable support for Rockchip LVDS controllers.
116 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
117 support LVDS, rgb, dual LVDS output mode. say Y to enable its
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-var-mx6customboard.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Support for Variscite MX6 Carrier-board
9 /dts-v1/;
11 #include "imx6qdl-var-som.dtsi"
12 #include <dt-bindings/pwm/pwm.h>
15 model = "Variscite i.MX6 QUAD/DUAL VAR-SOM-MX6 Custom Board";
16 compatible = "variscite,mx6customboard", "variscite,var-som-imx6q", "fsl,imx6q";
18 panel0: lvds-panel0 {
19 compatible = "panel-lvds";
21 width-mm = <152>;
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H A Dimx6q-display5-tianma-tm070-1280x768.dts5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
38 /dts-v1/;
40 #include "imx6q-display5.dtsi"
47 lvds0: lvds-channel@0 {
48 fsl,data-mapping = "spwg";
49 fsl,data-width = <18>;
H A Dimx6dl-aristainetos2_7.dts6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
43 /dts-v1/;
45 #include "imx6qdl-aristainetos2.dtsi"
48 model = "aristainetos2 i.MX6 Dual Lite Board 7";
49 compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl";
59 enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
63 remote-endpoint = <&lvds0_out>;
73 interrupt-parent = <&gpio2>;
81 lvds-channel@0 {
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/linux/arch/powerpc/sysdev/
H A Dfsl_soc.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 static inline u32 get_brgfreq(void) { return -1; } in get_brgfreq()
16 static inline u32 get_baudrate(void) { return -1; } in get_baudrate()
26 FSL_DIU_PORT_LVDS, /* Single-link LVDS */
27 FSL_DIU_PORT_DLVDS /* Dual-link LVDS */
/linux/Documentation/fb/
H A Dviafb.rst6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_encoder.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Encoder
5 * Copyright (C) 2013-2014 Renesas Electronics Corporation
21 /* -----------------------------------------------------------------------------
70 bridge = devm_drm_panel_bridge_add_typed(rcdu->dev, panel, in rcar_du_encoder_init()
77 return -EPROBE_DEFER; in rcar_du_encoder_init()
81 rcdu->lvds[output - RCAR_DU_OUTPUT_LVDS0] = bridge; in rcar_du_encoder_init()
85 rcdu->dsi[output - RCAR_DU_OUTPUT_DSI0] = bridge; in rcar_du_encoder_init()
90 * the LVDS1 encoder is used as a companion for LVDS0 in dual-link in rcar_du_encoder_init()
91 * mode, or any LVDS output if it isn't connected. The latter may happen in rcar_du_encoder_init()
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/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
48 /* The single-channel range is 25-112Mhz, and dual-channel
49 * is 80-224Mhz. Prefer single channel as much as possible.
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
71 clock->p = clock->p1 * clock->p2; in psb_intel_clock()
72 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
73 clock->dot = clock->vco / clock->p; in psb_intel_clock()
78 * or -1 if the panel fitter is not present or not in use
88 return -1; in psb_intel_panel_fitter_pipe()
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H A Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
293 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bios.c2 * Copyright 2005-2006 Erik Waling
4 * Copyright 2007-2009 Stuart Bennett
33 #include <linux/io-mapping.h>
43 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
69 if (bios->major_version < 5) /* pre BIT */ in clkcmptable()
75 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); in clkcmptable()
77 if (bios->major_version < 5) { in clkcmptable()
78 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; in clkcmptable()
79 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); in clkcmptable()
81 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); in clkcmptable()
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