dram\-controller (full) in projects: linux

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/linux/Documentation/devicetree/bindings/memory-controllers/
H A D	rockchip,rk3399-dmc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip rk3399 DMC (Dynamic Memory Controller) device 10 - Brian Norris <briannorris@chromium.org> 15 - rockchip,rk3399-dmc 17 devfreq-events: 26 clock-names: 28 - const: dmc_clk [all …]`
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	uncore-memory.json	3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd", 8 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… 14 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 19 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p… 25 "BriefDescription": "DRAM Activate Count : All Activates", 30 …DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha… 35 "BriefDescription": "DRAM Activate Count : Activate due to Bypass", 41 …DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on… 46 "BriefDescription": "All DRAM CAS commands issued", 51 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.", [all …]
/linux/Documentation/devicetree/bindings/arm/sunxi/
H A D	allwinner,sun4i-a10-mbus.yaml	1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner Memory Bus (MBUS) controller 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 The MBUS controller drives the MBUS that other devices in the SoC 20 the interconnects and interconnect-names properties set to the MBUS 21 controller and with "dma-mem" as the interconnect name. [all …]
/linux/drivers/memory/tegra/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0-only 3 bool "NVIDIA Tegra Memory Controller support" 8 This driver supports the Memory Controller (MC) hardware found on 14 tristate "NVIDIA Tegra20 External Memory Controller driver" 21 This driver is for the External Memory Controller (EMC) found on 22 Tegra20 chips. The EMC controls the external DRAM on the board. 27 tristate "NVIDIA Tegra30 External Memory Controller driver" 33 This driver is for the External Memory Controller (EMC) found on 34 Tegra30 chips. The EMC controls the external DRAM on the board. 39 tristate "NVIDIA Tegra124 External Memory Controller driver" [all …]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	uncore-memory.json	3 "BriefDescription": "DRAM Activate Count : All Activates", 8 …DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha… 13 "BriefDescription": "DRAM Activate Count : Activate due to Bypass", 19 …DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on… 24 "BriefDescription": "All DRAM CAS commands issued", 29 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.", 34 "BriefDescription": "All DRAM read CAS commands issued (including underfills)", 39 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu… 44 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre", 50 …ption": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_C… [all …]
H A D	other.json	3 … where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 7 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX… 16 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct… 25 …running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). … 103 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 106 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 113 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 123 …e prefetches that were supplied by DRAM on a distant memory controller of this socket when the sys… 143 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 146 "EventName": "OCR.DEMAND_DATA_RD.DRAM", [all …]
/linux/drivers/edac/
H A D	i3000_edac.c	2 * Intel 3000/3010 Memory Controller kernel module 5 * Intel D82875P Memory Controller kernel module 25 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller / 31 #define I3000_EDEAP 0x70 / Extended DRAM Error Address Pointer (8b) 36 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b) 54 deap \|= (edeap & 1) << (32 - PAGE_SHIFT); in deap_pfn() 60 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK; in deap_offset() 68 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b) 70 * 7:0 DRAM ECC Syndrome 79 * 9 LOCK to non-DRAM Memory Flag (LCKF) [all …]
H A D	amd64_edac.h	2 * AMD64 class Memory Controller kernel module 5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc. 57 * is within a range affected by memory hoisting. The DRAM Base 58 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers 61 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr 77 * memory controller for the node that the DramAddr is associated 78 * with. The memory controller then maps the InputAddr to a csrow. 84 * The memory controller for a given node uses its DRAM CS Base and 85 * DRAM CS Mask registers to map an InputAddr to a csrow. See 105 * PCI-defined configuration space registers [all …]
H A D	i82975x_edac.c	2 * Intel 82975X Memory Controller kernel module 34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller / 35 #define I82975X_EAP 0x58 / Dram Error Address Pointer (32b) 37 * 31:7 128 byte cache-line address 42 #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b) 44 * 7:0 DRAM ECC Syndrome 47 #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b) 50 * More - See Page 65 of Intel DocSheet. 58 * 9 non-DRAM lock error (ndlock) 61 * 1 ECC UE (multibit DRAM error) [all …]
H A D	altera_edac.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 3 Copyright (C) 2017-2018, Intel Corporation 10 #include <linux/arm-smccc.h> 14 /* SDRAM Controller CtrlCfg Register / 17 / SDRAM Controller CtrlCfg Register Bit Masks / 25 / SDRAM Controller Address Width Register / 28 / SDRAM Controller Address Widths Field Register / 38 / SDRAM Controller Interface Data Width Register / 41 / SDRAM Controller Interface Data Width Defines / 45 / SDRAM Controller DRAM Status Register */ [all …]`
H A D	i82875p_edac.c	2 * Intel D82875P Memory Controller kernel module 13 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com 43 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller / 50 #define I82875P_DERRSYN 0x5c / DRAM Error Syndrome (8b) 52 * 7:0 DRAM ECC Syndrome 55 #define I82875P_DES 0x5d /* DRAM Error Status (8b) 64 * 9 non-DRAM lock error (ndlock) 79 * 9 SERR on non-DRAM lock 91 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller / 95 9 fast back-to-back - ro 0 [all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A D	uncore-memory.json	3 "BriefDescription": "DRAM Activate Count", 8 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued… 12 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)", 21 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)", 30 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)", 39 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued", 48 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)", 57 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read… 66 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Writ… 79 "PublicDescription": "Uncore Fixed Counter - uclks", [all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	uncore-memory.json	3 …: "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activa… 12 …DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Acti… 22 …DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of… 32 …DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Act… 97 "BriefDescription": "CAS count for SubChannel 0 auto-precharge writes", 162 "BriefDescription": "CAS count for SubChannel 1 auto-precharge writes", 172 "BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled", 177 "PublicDescription": "DRAM Clockticks", 182 "BriefDescription": "Number of DRAM HCLK clock cycles while the event is enabled", 188 "PublicDescription": "DRAM Clockticks", [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	uncore-memory.json	3 …: "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activa… 12 …DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Acti… 22 …DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of… 32 …DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Act… 97 "BriefDescription": "CAS count for SubChannel 0 auto-precharge writes", 162 "BriefDescription": "CAS count for SubChannel 1 auto-precharge writes", 172 "BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled", 177 "PublicDescription": "DRAM Clockticks", 182 "BriefDescription": "Number of DRAM HCLK clock cycles while the event is enabled", 188 "PublicDescription": "DRAM Clockticks", [all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	uncore-memory.json	3 …: "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activa… 12 …DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Acti… 22 …DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of… 32 …DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Act… 97 "BriefDescription": "CAS count for SubChannel 0 auto-precharge writes", 162 "BriefDescription": "CAS count for SubChannel 1 auto-precharge writes", 172 "BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled", 177 "PublicDescription": "DRAM Clockticks", 182 "BriefDescription": "Number of DRAM HCLK clock cycles while the event is enabled", 188 "PublicDescription": "DRAM Clockticks", [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	other.json	29 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 32 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 39 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 49 …e prefetches that were supplied by DRAM on a distant memory controller of this socket when the sys… 69 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 72 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 79 …ds that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 89 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke… 99 …d data reads that were supplied by DRAM on a distant memory controller of this socket when the sys… 119 … requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", [all …]
H A D	uncore-memory.json	3 "BriefDescription": "Cycles - at UCLK", 228 "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", 238 "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", 248 "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", 258 "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", 348 "BriefDescription": "Multi-socket cacheline Directory update from A to I", 358 "BriefDescription": "Multi-socket cacheline Directory update from A to S", 368 "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", 377 "BriefDescription": "Multi-socket cacheline Directory Updates", 390 "BriefDescription": "Multi-socket cacheline Directory Updates", [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	other.json	29 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 32 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 39 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 49 …e prefetches that were supplied by DRAM on a distant memory controller of this socket when the sys… 69 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 72 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 79 …ds that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S… 109 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke… 129 …d data reads that were supplied by DRAM on a distant memory controller of this socket when the sys… 149 … requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", [all …]
H A D	uncore-memory.json	3 "BriefDescription": "Cycles - at UCLK", 228 "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", 238 "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", 248 "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", 258 "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", 348 "BriefDescription": "Multi-socket cacheline Directory update from A to I", 358 "BriefDescription": "Multi-socket cacheline Directory update from A to S", 368 "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", 377 "BriefDescription": "Multi-socket cacheline Directory Updates", 390 "BriefDescription": "Multi-socket cacheline Directory Updates", [all …]
/linux/Documentation/driver-api/
H A D	edac.rst	5 ---------------------------------------- 8 sockets, socket sets, banks, rows, chip-select rows, channels, 18 The individual DRAM chips on a memory stick. These devices commonly 20 provides the number of bits that the memory controller expects: 37 A memory controller channel, responsible to communicate with a group of 43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory 44 controller. Typically, it contains two channels. Two channels at the 52 Single-channel 54 The data accessed by the memory controller is contained into one dimm 55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A D	recommended.json	4 "BriefDescription": "Execution-time branch misprediction ratio (non-speculative).", 120 "BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.", 168 "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node.", 180 "BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node.", 216 "BriefDescription": "Macro-ops dispatched.", 227 "BriefDescription": "Macro-ops retired.", 232 "BriefDescription": "DRAM read data for local processor.", 236 "ScaleUnit": "6.103515625e-5MiB" 240 "BriefDescription": "DRAM write data for local processor.", 244 "ScaleUnit": "6.103515625e-5MiB" [all …]
/linux/drivers/memory/samsung/
H A D	Kconfig	1 # SPDX-License-Identifier: GPL-2.0 3 bool "Samsung Exynos Memory Controller support" if COMPILE_TEST 5 Support for the Memory Controller (MC) devices found on 11 tristate "Exynos5422 Dynamic Memory Controller driver" 18 Controller). The driver provides support for Dynamic Voltage and 19 Frequency Scaling in DMC and DRAM. It also supports changing timings 20 of DRAM running with different frequency. The timings are calculated 25 bool "Exynos SROM controller driver" if COMPILE_TEST 28 This adds driver for Samsung Exynos SoC SROM controller. The driver
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	uncore-memory.json	3 "BriefDescription": "DRAM Activate Count; Activate due to Write", 8 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued… 13 "BriefDescription": "DRAM Activate Count; Activate due to Read", 18 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued… 23 "BriefDescription": "DRAM Activate Count; Activate due to Write", 28 …: "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued… 60 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)", 65 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command… 70 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)", 75 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co… [all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A D	cortina,gemini-pinctrl.txt	1 Cortina Systems Gemini pin controller 3 This pin controller is found in the Cortina Systems Gemini SoC family, 4 see further arm/gemini.txt. It is a purely group-based multiplexing pin 5 controller. 7 The pin controller node must be a subnode of the system controller node. 10 - compatible: "cortina,gemini-pinctrl" 12 Subnodes of the pin controller contain pin control multiplexing set-up 15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes 19 - skew-delay is supported on the Ethernet pins 20 - drive-strength with 4, 8, 12 or 16 mA as argument is supported for [all …]
/linux/drivers/usb/host/
H A D	xhci-mvebu.c	1 // SPDX-License-Identifier: GPL-2.0 4 * Author: Gregory CLEMENT <gregory.clement@free-electrons.com> 15 #include "xhci-mvebu.h" 23 const struct mbus_dram_target_info dram) in xhci_mvebu_mbus_config() argument 33 / Program each DRAM CS in a seperate window / in xhci_mvebu_mbus_config() 34 for (win = 0; win < dram->num_cs; win++) { in xhci_mvebu_mbus_config() 35 const struct mbus_dram_window cs = &dram->cs[win]; in xhci_mvebu_mbus_config() 37 writel(((cs->size - 1) & 0xffff0000) \| (cs->mbus_attr << 8) \| in xhci_mvebu_mbus_config() 38 (dram->mbus_dram_target_id << 4) \| 1, in xhci_mvebu_mbus_config() 41 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); in xhci_mvebu_mbus_config() [all …]

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