2  * Intel 82975X Memory Controller kernel module
34 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
35 #define I82975X_EAP		0x58	/* Dram Error Address Pointer (32b)
37 					 * 31:7  128 byte cache-line address
42 #define I82975X_DERRSYN		0x5c	/* Dram Error SYNdrome (8b)
44 					 *  7:0  DRAM ECC Syndrome
47 #define I82975X_DES		0x5d	/* Dram ERRor DeSTination (8b)
50 					 * More - See Page 65 of Intel DocSheet.
58 					 *  9    non-DRAM lock error (ndlock)
61 					 *  1    ECC UE (multibit DRAM error)
62 					 *  0    ECC CE (singlebit DRAM error)
76 					 *  9    non-DRAM lock error (ndlock)
79 					 *  1    ECC UE (multibit DRAM error)
80 					 *  0    ECC CE (singlebit DRAM error)
86 					 *  1    ECC UE (multibit DRAM error)
87 					 *  0    ECC CE (singlebit DRAM error)
93 					 *  1    ECC UE (multibit DRAM error)
94 					 *  0    ECC CE (singlebit DRAM error)
97 #define I82975X_XEAP	0xfc	/* Extended Dram Error Address Pointer (8b)
100 					 * 0     Bit32 of the Dram Error Address
105 					 * 31:14 Base Addr of 16K memory-mapped
108 					 *  0    mem-mapped config space enable
116 #define I82975X_DRB		0x100	/* DRAM Row Boundary (8b x 8)
134 #define I82975X_DRA		0x108	/* DRAM Row Attribute (4b x 8)
155 #define I82975X_BNKARC	0x10e /* Type of device in each rank - Bank Arch (16b)
171 #define I82975X_DRC		0x120 /* DRAM Controller Mode0 (32b)
187 					 *  1:0  DRAM type 10=Second Revision
195 #define I82975X_DRC_M1	0x124 /* DRAM Controller Mode1 (32b)
243 	pdev = to_pci_dev(mci->pdev);  in i82975x_get_error_info()
250 	pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);  in i82975x_get_error_info()
251 	pci_read_config_dword(pdev, I82975X_EAP, &info->eap);  in i82975x_get_error_info()
252 	pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);  in i82975x_get_error_info()
253 	pci_read_config_byte(pdev, I82975X_DES, &info->des);  in i82975x_get_error_info()
254 	pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);  in i82975x_get_error_info()
255 	pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);  in i82975x_get_error_info()
265 	if (!(info->errsts2 & 0x0003))  in i82975x_get_error_info()
268 	if ((info->errsts ^ info->errsts2) & 0x0003) {  in i82975x_get_error_info()
269 		pci_read_config_dword(pdev, I82975X_EAP, &info->eap);  in i82975x_get_error_info()
270 		pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);  in i82975x_get_error_info()
271 		pci_read_config_byte(pdev, I82975X_DES, &info->des);  in i82975x_get_error_info()
273 				&info->derrsyn);  in i82975x_get_error_info()
283 	if (!(info->errsts2 & 0x0003))  in i82975x_process_error_info()
289 	if ((info->errsts ^ info->errsts2) & 0x0003) {  in i82975x_process_error_info()
291 				     -1, -1, -1, "UE overwrote CE", "");  in i82975x_process_error_info()
292 		info->errsts = info->errsts2;  in i82975x_process_error_info()
295 	page = (unsigned long) info->eap;  in i82975x_process_error_info()
297 	if (info->xeap & 1)  in i82975x_process_error_info()
299 	page >>= (PAGE_SHIFT - 1);  in i82975x_process_error_info()
302 	if (row == -1)	{  in i82975x_process_error_info()
307 			(info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);  in i82975x_process_error_info()
310 	chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1;  in i82975x_process_error_info()
311 	offst = info->eap  in i82975x_process_error_info()
312 			& ((1 << PAGE_SHIFT) -  in i82975x_process_error_info()
313 			   (1 << mci->csrows[row]->channels[chan]->dimm->grain));  in i82975x_process_error_info()
315 	if (info->errsts & 0x0002)  in i82975x_process_error_info()
318 				     row, -1, -1,  in i82975x_process_error_info()
322 				     page, offst, info->derrsyn,  in i82975x_process_error_info()
323 				     row, chan ? chan : 0, -1,  in i82975x_process_error_info()
341 	 * We treat interleaved-symmetric configuration as dual-channel - EAP's  in dual_channel_active()
342 	 * bit-0 giving the channel of the error location.  in dual_channel_active()
344 	 * All other configurations are treated as single channel - the EAP's  in dual_channel_active()
345 	 * bit-0 will resolve ok in symmetric area of mixed  in dual_channel_active()
374 	 * The dram row boundary (DRB) reg values are boundary address  in i82975x_init_csrows()
375 	 * for each DRAM row with a granularity of 32 or 64MB (single/dual  in i82975x_init_csrows()
381 	for (index = 0; index < mci->nr_csrows; index++) {  in i82975x_init_csrows()
382 		csrow = mci->csrows[index];  in i82975x_init_csrows()
387 		cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);  in i82975x_init_csrows()
392 		if (csrow->nr_channels > 1)  in i82975x_init_csrows()
396 		nr_pages = cumul_size - last_cumul_size;  in i82975x_init_csrows()
401 		 * Initialise dram labels  in i82975x_init_csrows()
403 		 *   [0-7] for single-channel; i.e. csrow->nr_channels = 1  in i82975x_init_csrows()
404 		 *   [0-3] for dual-channel; i.e. csrow->nr_channels = 2  in i82975x_init_csrows()
406 		for (chan = 0; chan < csrow->nr_channels; chan++) {  in i82975x_init_csrows()
407 			dimm = mci->csrows[index]->channels[chan]->dimm;  in i82975x_init_csrows()
409 			dimm->nr_pages = nr_pages / csrow->nr_channels;  in i82975x_init_csrows()
411 			snprintf(csrow->channels[chan]->dimm->label, EDAC_MC_LABEL_LEN, "DIMM %c%d",  in i82975x_init_csrows()
414 			dimm->grain = 1 << 7;	/* 128Byte cache-line resolution */  in i82975x_init_csrows()
417 			dimm->dtype = DEV_X8;  in i82975x_init_csrows()
419 			dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */  in i82975x_init_csrows()
420 			dimm->edac_mode = EDAC_SECDED; /* only supported */  in i82975x_init_csrows()
423 		csrow->first_page = last_cumul_size;  in i82975x_init_csrows()
424 		csrow->last_page = cumul_size - 1;  in i82975x_init_csrows()
436 	 * (shows 13-5-5-5 for 800-DDR2)  in i82975x_print_dram_timings()
437 	 * Asus P5W Bios reports 15-5-4-4  in i82975x_print_dram_timings()
445 	i82975x_printk(KERN_INFO, "DRAM Timings :     Ch0    Ch1\n"  in i82975x_print_dram_timings()
465 	int rc = -ENODEV;  in i82975x_probe1()
539 	/* assuming only one controller, index thus is 0 */  in i82975x_probe1()
548 		rc = -ENOMEM;  in i82975x_probe1()
553 	mci->pdev = &pdev->dev;  in i82975x_probe1()
554 	mci->mtype_cap = MEM_FLAG_DDR2;  in i82975x_probe1()
555 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;  in i82975x_probe1()
556 	mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;  in i82975x_probe1()
557 	mci->mod_name = EDAC_MOD_STR;  in i82975x_probe1()
558 	mci->ctl_name = i82975x_devs[dev_idx].ctl_name;  in i82975x_probe1()
559 	mci->dev_name = pci_name(pdev);  in i82975x_probe1()
560 	mci->edac_check = i82975x_check;  in i82975x_probe1()
561 	mci->ctl_page_to_phys = NULL;  in i82975x_probe1()
563 	pvt = (struct i82975x_pvt *) mci->pvt_info;  in i82975x_probe1()
564 	pvt->mch_window = mch_window;  in i82975x_probe1()
566 	mci->scrub_mode = SCRUB_HW_SRC;  in i82975x_probe1()
569 	/* finalize this instance of memory controller with edac core */  in i82975x_probe1()
597 		return -EIO;  in i82975x_init_one()
599 	rc = i82975x_probe1(pdev, ent->driver_data);  in i82975x_init_one()
614 	mci = edac_mc_del_mc(&pdev->dev);  in i82975x_remove_one()
618 	pvt = mci->pvt_info;  in i82975x_remove_one()
619 	if (pvt->mch_window)  in i82975x_remove_one()
620 		iounmap( pvt->mch_window );  in i82975x_remove_one()
663 			pci_rc = -ENODEV;  in i82975x_init()
671 			pci_rc = -ENODEV;  in i82975x_init()