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/linux/include/soc/at91/
H A Dsama7-ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
23 #define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */
24 #define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */
29 #define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
33 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
34 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
35 #define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
38 #define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
41 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
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/linux/Documentation/sound/
H A Dalsa-configuration.rst2 Advanced Linux Sound Architecture - Driver Configuration guide
38 ----------
47 limiting card index for auto-loading (1-8);
49 For auto-loading more than one card, specify this option
50 together with snd-card-X aliases.
57 (0 = disable debug prints, 1 = normal debug messages,
63 Module snd-pcm-oss
64 ------------------
86 regarding opening the device. When this option is non-zero,
90 Module snd-rawmidi
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/linux/arch/sparc/include/asm/
H A Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define CLOCK_CTRL 0x00UL /* Main control */
14 #define CLOCK_PWRSTAT 0x30UL /* Power status */
15 #define CLOCK_PWRPRES 0x40UL /* Power presence */
18 #define CLOCK_PWRSTAT2 0x70UL /* Power status two */
30 #define FHC_PREGS_RCS 0x10UL /* FHC Reset Control/Status Register */
31 #define FHC_RCS_POR 0x80000000 /* Last reset was a power cycle */
32 #define FHC_RCS_SPOR 0x40000000 /* Last reset was sw power on reset */
39 #define FHC_PREGS_CTRL 0x20UL /* FHC Control Register */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
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/linux/Documentation/driver-api/usb/
H A Dpower-management.rst1 .. _usb-power-management:
3 Power Management for USB
7 :Date: Last-updated: February 2014
11 ---------
12 * What is Power Management?
17 * Changing the default idle-delay time
19 * The driver interface for Power Management
25 * USB Port Power Control
26 * User Interface for Port Power Control
27 * Suggested Userspace Port Power Policy
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/linux/drivers/net/ethernet/marvell/
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
39 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
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/linux/Documentation/devicetree/bindings/usb/
H A Dpxa-usb.txt6 - compatible: Should be "marvell,pxa-ohci" for USB controllers
10 - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
11 If present, enables the appropriate USB port of the controller.
12 - "marvell,port-mode" selects the mode of the ports:
16 - "marvell,power-sense-low" - power sense pin is low-active.
17 - "marvell,power-control-low" - power control pin is low-active.
18 - "marvell,no-oc-protection" - disable over-current protection.
19 - "marvell,oc-mode-perport" - enable per-port over-current protection.
20 - "marvell,power_on_delay" Power On to Power Good time - in ms.
25 compatible = "marvell,pxa-ohci";
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H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
17 The DRD controller has a glue layer IPPC (IP Port Control), and its host is
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
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H A Dfsl,imx8mp-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Li Jun <jun.li@nxp.com>
16 - items:
17 - const: fsl,imx95-dwc3
18 - const: fsl,imx8mp-dwc3
19 - const: fsl,imx8mp-dwc3
23 - description: Address and length of the register set for HSIO Block Control
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H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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/linux/drivers/bus/
H A Darm-cci.c17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
67 #define DRIVER_NAME "ARM-CCI"
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/linux/drivers/pci/hotplug/
H A Dpciehp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
8 * Copyright (C) 2003-2004 Intel Corporation
36 pci_dbg(ctrl->pcie->port, format, ## arg)
38 pci_err(ctrl->pcie->port, format, ## arg)
40 pci_info(ctrl->pcie->port, format, ## arg)
42 pci_warn(ctrl->pcie->port, format, ## arg)
47 * struct controller - PCIe hotplug controller
48 * @pcie: pointer to the controller's PCIe port service device
53 * @inband_presence_disabled: In-Band Presence Detect Disable supported by
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt13 Advanced Configuration and Power Interface
16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
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/linux/include/uapi/linux/
H A Dpci_regs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
51 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */
124 /* 0x35-0x3b are reserved */
130 /* Header type 1 (PCI-to-PCI bridges) */
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/linux/arch/sh/drivers/pci/
H A Dpci-sh4.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include "pci-sh7780.h"
10 #include "pci-sh7751.h"
15 #define SH4_PCICR 0x100 /* PCI Control Register */
35 #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
40 #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
41 #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
45 #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
47 #define SH4_PCIINTM_MDEIM BIT(8) /* Master function disable error */
81 #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
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/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
77 * Universal Serial Bus (USB) Device Controller (UDC) control registers
80 * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
81 * Controller (UDC) Control Register (read/write).
82 * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
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/linux/include/linux/usb/
H A Dehci_def.h1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2001-2002 by David Brownell
9 #include <linux/usb/ehci-dbgp.h>
17 * some hosts treat caplength and hciversion as parts of a 32-bit
26 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
27 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
28 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
31 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
32 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
34 #define HCS_N_PORTS_MAX 15 /* N_PORTS valid 0x1-0xF */
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/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l35.txt5 - compatible : "cirrus,cs35l35"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - interrupts : IRQ line info CS35L35.
14 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - cirrus,boost-ind-nanohenry: Inductor value for boost converter. The value is
21 - reset-gpios : gpio used to reset the amplifier
23 - cirrus,stereo-config : Boolean to determine if there are 2 AMPs for a
26 - cirrus,audio-channel : Set Location of Audio Signal on Serial Port
30 - cirrus,advisory-channel : Set Location of Advisory Signal on Serial Port
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/linux/drivers/usb/host/
H A Dpci-quirks.c1 // SPDX-License-Identifier: GPL-2.0
4 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
5 * It may need to run early during booting -- before USB would normally
6 * initialize -- to ensure that Linux doesn't use any legacy modes.
22 #include "pci-quirks.h"
23 #include "xhci-ext-caps.h"
60 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
146 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
156 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; in amd_chipset_sb_type_init()
158 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, in amd_chipset_sb_type_init()
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H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
32 * control laws, including the U.S. Export Administration Act and its associated
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
172 * This value is in terms of 32-bit words.
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/linux/drivers/net/phy/
H A Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include "bcm-phy-lib.h"
16 /* RDB per-port registers
23 #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */
25 #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */
26 #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */
28 #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */
30 #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */
33 #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */
35 #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-usb10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
33 Contact: linux-usb@vger.kernel.org
67 What: /sys/bus/usb-serial/drivers/.../new_id
69 Contact: linux-usb@vger.kernel.org
72 extra bus folder "usb-serial" in sysfs; apart from that
93 What: /sys/bus/usb/devices/.../power/usb2_hardware_lpm
97 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
102 power/usb2_hardware_lpm. The file holds a string value (enable
103 or disable) indicating whether or not USB2 hardware LPM is
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/linux/drivers/net/ethernet/intel/e1000e/
H A D82571.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * 82571EB Dual Port Gigabit Mezzanine Adapter
8 * 82571EB Quad Port Gigabit Mezzanine Adapter
9 * 82571PT Gigabit PT Quad Port Server ExpressModule
42 * e1000_init_phy_params_82571 - Init PHY func ptrs.
47 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82571()
50 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82571()
51 phy->type = e1000_phy_none; in e1000_init_phy_params_82571()
55 phy->addr = 1; in e1000_init_phy_params_82571()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
18 (port mode) or in alternate function mode.
24 - items:
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/linux/include/sound/
H A Dcs4231-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #define CS4231_LEFT_INPUT 0x00 /* left input control */
22 #define CS4231_RIGHT_INPUT 0x01 /* right input control */
23 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
24 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
25 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
26 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
27 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
28 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
29 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
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