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/linux/drivers/clk/meson/
H A Ds4-pll.c1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-mpll.h"
14 #include "clk-pll.h"
15 #include "clk-regmap.h"
16 #include "meson-clkc-utils.h"
17 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
50 * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
55 .data = &(struct meson_clk_pll_data){
[all …]
H A Da1-peripherals.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
12 #include "clk-dualdiv.h"
13 #include "clk-regmap.h"
14 #include "meson-clkc-utils.h"
16 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
49 .data = &(struct clk_regmap_gate_data){
64 .data = &(struct clk_regmap_gate_data){
79 .data = &(struct clk_regmap_gate_data){
94 .data = &(struct clk_regmap_gate_data){
[all …]
H A Daxg.c1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
17 #include "clk-regmap.h"
18 #include "clk-pll.h"
19 #include "clk-mpll.h"
20 #include "meson-clkc-utils.h"
22 #include <dt-bindings/clock/axg-clkc.h>
111 .data = &(struct meson_clk_pll_data){
114 .shift = 30,
[all …]
H A Dgxbb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
13 #include "clk-pll.h"
14 #include "clk-mpll.h"
15 #include "meson-clkc-utils.h"
16 #include "vid-pll-div.h"
18 #include <dt-bindings/clock/gxbb-clkc.h>
119 .data = &(struct meson_clk_pll_data){
122 .shift = 30,
[all …]
H A Dc3-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
12 #include "clk-pll.h"
13 #include "meson-clkc-utils.h"
14 #include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
38 .data = &(struct clk_regmap_gate_data) {
79 .data = &(struct clk_regmap_gate_data) {
107 .data = &(struct clk_regmap_gate_data) {
135 .data = &(struct clk_regmap_gate_data) {
[all …]
H A Dg12a-aoclk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
16 #include "meson-aoclk.h"
18 #include "clk-regmap.h"
19 #include "clk-dualdiv.h"
21 #include <dt-bindings/clock/g12a-aoclkc.h>
22 #include <dt-bindings/reset/g12a-aoclkc.h>
26 * Register offsets from the data sheet must be multiplied by 4.
[all …]
H A Dmeson8b.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
19 #include "clk-regmap.h"
20 #include "meson-clkc-utils.h"
21 #include "clk-pll.h"
22 #include "clk-mpll.h"
24 #include <dt-bindings/clock/meson8b-clkc.h>
25 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
30 * Register offsets from the HardKernel[0] data sheet must be multiplied
[all …]
H A Dclk-regmap.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
15 * struct clk_regmap - regmap backed clock
17 * @hw: handle between common and hardware-specific interfaces
19 * @data: data specific to the clock type
22 * of the clock is controlled by the clock_ops and data.
27 void *data; member
39 * struct clk_regmap_gate_data - regmap backed gate specific data
43 * @flags: hardware-specific flags
57 return (struct clk_regmap_gate_data *)clk->data; in clk_get_regmap_gate_data()
[all …]
H A Da1-pll.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
12 #include "clk-pll.h"
13 #include "clk-regmap.h"
14 #include "meson-clkc-utils.h"
26 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
29 .data = &(struct meson_clk_pll_data){
32 .shift = 28,
37 .shift = 0,
42 .shift = 10,
[all …]
/linux/arch/arm64/lib/
H A Dcsum.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 Arm Ltd.
5 #include <linux/kasan-checks.h>
10 /* Looks dumb, but generates nice-ish code */
11 static u64 accumulate(u64 sum, u64 data) in accumulate() argument
13 __uint128_t tmp = (__uint128_t)sum + data; in accumulate()
18 * We over-read the buffer and this makes KASAN unhappy. Instead, disable
23 unsigned int offset, shift, sum; in do_csum() local
25 u64 data, sum64 = 0; in do_csum() local
34 * should absolutely not be pointing to anything read-sensitive. We do, in do_csum()
[all …]
/linux/arch/sh/drivers/pci/
H A Dops-sh4.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
5 * Copyright (C) 2002 - 2009 Paul Mundt
11 #include "pci-sh4.h"
17 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
25 struct pci_channel *chan = bus->sysdata; in sh4_pci_read()
27 u32 data; in sh4_pci_read() local
35 data = pci_read_reg(chan, SH4_PCIPDR); in sh4_pci_read()
40 *val = (data >> ((where & 3) << 3)) & 0xff; in sh4_pci_read()
43 *val = (data >> ((where & 2) << 3)) & 0xffff; in sh4_pci_read()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A Dnv50.c29 struct nvkm_device *device = gpio->subdev.device; in nv50_gpio_reset()
30 struct nvkm_bios *bios = device->bios; in nv50_gpio_reset()
33 int ent = -1; in nv50_gpio_reset()
37 u32 data = nvbios_rd32(bios, entry); in nv50_gpio_reset() local
38 u8 line = (data & 0x0000001f); in nv50_gpio_reset()
39 u8 func = (data & 0x0000ff00) >> 8; in nv50_gpio_reset()
40 u8 defs = !!(data & 0x01000000); in nv50_gpio_reset()
41 u8 unk0 = !!(data & 0x02000000); in nv50_gpio_reset()
42 u8 unk1 = !!(data & 0x04000000); in nv50_gpio_reset()
58 nv50_gpio_location(int line, u32 *reg, u32 *shift) in nv50_gpio_location() argument
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
116 .eint_mask = (1 << (pins)) - 1, \
140 .eint_mask = (1 << (pins)) - 1, \
194 .eint_mask = (1 << (pins)) - 1, \
200 * struct s3c64xx_eint0_data - EINT0 common data
201 * @drvdata: pin controller driver data
212 * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
[all …]
/linux/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable()
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable()
298 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; sprd_mcdt_dac_dma_ack_select() local
320 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; sprd_mcdt_adc_dma_ack_select() local
342 u32 reg, shift; sprd_mcdt_chan_fifo_sts() local
395 u32 shift = MCDT_ADC_FIFO_SHIFT + channel; sprd_mcdt_adc_fifo_clear() local
456 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); sprd_mcdt_chan_int_en() local
481 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); sprd_mcdt_chan_int_clear() local
503 u32 reg, shift = sprd_mcdt_int_type_shift(channel, int_type); sprd_mcdt_chan_int_sts() local
[all...]
/linux/arch/riscv/lib/
H A Dcsum.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2023-2024 Rivos Inc.
11 #include <linux/kasan-checks.h>
27 sum += (__force unsigned long)saddr->s6_addr32[0]; in csum_ipv6_magic()
28 sum += (__force unsigned long)saddr->s6_addr32[1]; in csum_ipv6_magic()
29 sum += (__force unsigned long)saddr->s6_addr32[2]; in csum_ipv6_magic()
30 sum += (__force unsigned long)saddr->s6_addr32[3]; in csum_ipv6_magic()
32 sum += (__force unsigned long)daddr->s6_addr32[0]; in csum_ipv6_magic()
33 sum += (__force unsigned long)daddr->s6_addr32[1]; in csum_ipv6_magic()
34 sum += (__force unsigned long)daddr->s6_addr32[2]; in csum_ipv6_magic()
[all …]
/linux/sound/pci/emu10k1/
H A Demu10k1_patch.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 * allocate a sample block and copy data from userspace
27 const void __user *data, long count) in snd_emu10k1_sample_new() argument
31 int shift; in snd_emu10k1_sample_new() local
37 emu = rec->hw; in snd_emu10k1_sample_new()
39 return -EINVAL; in snd_emu10k1_sample_new()
41 if (sp->v.mode_flags & (SNDRV_SFNT_SAMPLE_BIDIR_LOOP | SNDRV_SFNT_SAMPLE_REVERSE_LOOP)) { in snd_emu10k1_sample_new()
42 /* should instead return -ENOTSUPP; but compatibility */ in snd_emu10k1_sample_new()
43 dev_warn(emu->card->dev, in snd_emu10k1_sample_new()
45 sp->v.sample); in snd_emu10k1_sample_new()
[all …]
/linux/arch/arm/mach-omap2/
H A Dvc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
26 * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
27 * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
28 * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
29 * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
30 * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
31 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
32 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
[all …]
/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
19 #define div_mask(width) ((1 << (width)) - 1)
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
26 * @shift: shift to the divider bit field
35 u8 shift; member
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
[all …]
/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_ci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * DVB CAM support for NetUP Universal Dual DVB-CI
43 /* BIT_CAM_BYPASS bit shift for SLOT 1 */
48 writew(0x101, ndev->bmmio0 + CAM_CTRLSTAT_CLR); in netup_ci_interrupt()
55 struct netup_ci_state *state = en50221->data; in netup_unidvb_ci_slot_ts_ctl()
56 struct netup_unidvb_dev *dev = state->dev; in netup_unidvb_ci_slot_ts_ctl()
57 u16 shift = (state->nr == 1) ? CAM1_SHIFT : 0; in netup_unidvb_ci_slot_ts_ctl() local
59 dev_dbg(&dev->pci_dev->dev, "%s(): CAM_CTRLSTAT=0x%x\n", in netup_unidvb_ci_slot_ts_ctl()
60 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
62 return -EINVAL; in netup_unidvb_ci_slot_ts_ctl()
[all …]
/linux/sound/soc/codecs/
H A Dpcm6240.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2022 - 2024 Texas Instruments Incorporated
12 // Author: Shenghao Ding <shenghao-ding@ti.com>
64 .shift = 1,
70 .shift = 1,
79 .shift = 0,
85 .shift = 0,
94 .shift
604 unsigned int shift = mc->shift; pcmdev_get_volsw() local
677 unsigned int shift = mc->shift; pcmdev_put_volsw() local
1087 pcmdev_dev_bulk_write(struct pcmdevice_priv * pcm_dev,unsigned int dev_no,unsigned int reg,unsigned char * data,unsigned int len) pcmdev_dev_bulk_write() argument
1687 pcmdev_single_byte_wr(struct pcmdevice_priv * pcm_dev,unsigned char * data,int devn,int sublocksize) pcmdev_single_byte_wr() argument
1716 pcmdev_burst_wr(struct pcmdevice_priv * pcm_dev,unsigned char * data,int devn,int sublocksize) pcmdev_burst_wr() argument
1747 pcmdev_delay(struct pcmdevice_priv * pcm_dev,unsigned char * data,int devn,int sublocksize) pcmdev_delay() argument
1765 pcmdev_bits_wr(struct pcmdevice_priv * pcm_dev,unsigned char * data,int devn,int sublocksize) pcmdev_bits_wr() argument
1788 pcmdevice_process_block(void * ctxt,unsigned char * data,unsigned char dev_idx,int sublocksize) pcmdevice_process_block() argument
[all...]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-jtag.c8 * Copyright (c) 2003-2008 Cavium Networks
15 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <asm/octeon/cvmx-helper-jtag.h>
50 uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); in cvmx_helper_qlm_jtag_init()
51 divisor = (divisor - 1) >> 2; in cvmx_helper_qlm_jtag_init()
52 /* Convert the divisor into a power of 2 shift */ in cvmx_helper_qlm_jtag_init()
75 * into the MSB and out the LSB, so you should shift in the low
79 * @qlm: QLM to shift value into
80 * @bits: Number of bits to shift in (1-32).
[all …]
/linux/drivers/mfd/
H A Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #include <linux/mfd/syscon/atmel-smc.h>
21 * atmel_smc_cs_conf_init - initialize a SMC CS conf
33 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
46 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
55 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
56 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
71 * We still return -ERANGE in case the caller cares. in atmel_smc_cs_encode_ncycles()
76 ret = -ERANGE; in atmel_smc_cs_encode_ncycles()
[all …]
/linux/drivers/net/usb/
H A Dr8153_ecm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 u8 shift = index & 2; in pla_read_word() local
19 if (shift) in pla_read_word()
20 byen <<= shift; in pla_read_word()
30 ret >>= (shift * 8); in pla_read_word()
37 static int pla_write_word(struct usbnet *dev, u16 index, u32 data) in pla_write_word() argument
41 u8 shift = index & 2; in pla_write_word() local
45 data &= mask; in pla_write_word()
47 if (shift) { in pla_write_word()
48 byen <<= shift; in pla_write_word()
[all …]
/linux/net/sunrpc/
H A Dxdr.c1 // SPDX-License-Identifier: GPL-2.0-only
31 unsigned int quadlen = XDR_QUADLEN(obj->len); in xdr_encode_netobj()
34 *p++ = cpu_to_be32(obj->len); in xdr_encode_netobj()
35 memcpy(p, obj->data, obj->len); in xdr_encode_netobj()
36 return p + XDR_QUADLEN(obj->len); in xdr_encode_netobj()
41 * xdr_encode_opaque_fixed - Encode fixed length opaque data
43 * @ptr: pointer to data to encode (or NULL)
44 * @nbytes: size of data.
46 * Copy the array of data of length nbytes at ptr to the XDR buffer
47 * at position p, then align to the next 32-bit boundary by padding
[all …]
/linux/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
9 #include <dt-bindings/clock/clock.h>
17 * top-level framework. Custom flags for dealing with hardware specifics
20 * * CLK_SET_RATE_GATE - must be gated across rate change
21 * * CLK_SET_PARENT_GATE - must be gated across re-parent
22 * * CLK_SET_RATE_PARENT - propagate rate change up one level
23 * * CLK_IGNORE_UNUSED - do not gate even if unused
24 * * CLK_GET_RATE_NOCACHE - do not use the cached clk rate
[all …]

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