Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
26 #include "meson-eeclk.h"
29 #include <dt-bindings/clock/g12a-clkc.h>
32 .data = &(struct meson_clk_pll_data){
35 .shift = 28,
40 .shift = 0,
45 .shift = 10,
50 .shift = 0,
55 .shift = 31,
60 .shift = 29,
75 .data = &(struct clk_regmap_div_data){
77 .shift = 16,
101 .data = &(struct meson_clk_pll_data){
104 .shift = 28,
109 .shift = 0,
114 .shift = 10,
119 .shift = 31,
124 .shift = 29,
142 .data = &(struct clk_regmap_div_data){
144 .shift = 16,
160 .data = &(struct meson_clk_pll_data){
163 .shift = 28,
168 .shift = 0,
173 .shift = 10,
178 .shift = 31,
183 .shift = 29,
201 .data = &(struct clk_regmap_div_data){
203 .shift = 16,
219 .data = &(struct clk_regmap_gate_data){
236 .data = &(struct clk_regmap_gate_data){
292 .data = &(struct clk_regmap_gate_data){
310 * b) CCF has a clock hand-off mechanism to make the sure the
329 .data = &(struct clk_regmap_gate_data){
346 * b) CCF has a clock hand-off mechanism to make the sure the
355 .data = &(struct clk_regmap_mux_data){
358 .shift = 0,
376 .data = &(struct clk_regmap_mux_data){
379 .shift = 16,
390 /* This sub-tree is used a parking clock */
397 .data = &(struct meson_clk_cpu_dyndiv_data){
400 .shift = 4,
405 .shift = 26,
422 .data = &(struct clk_regmap_mux_data){
425 .shift = 2,
442 .data = &(struct clk_regmap_div_data){
444 .shift = 20,
459 .data = &(struct clk_regmap_mux_data){
462 .shift = 18,
472 /* This sub-tree is used a parking clock */
479 .data = &(struct clk_regmap_mux_data){
482 .shift = 10,
499 .data = &(struct clk_regmap_mux_data){
502 .shift = 11,
519 .data = &(struct clk_regmap_mux_data){
522 .shift = 11,
539 .data = &(struct clk_regmap_mux_data){
542 .shift = 0,
560 .data = &(struct meson_clk_cpu_dyndiv_data){
563 .shift = 4,
568 .shift = 26,
585 .data = &(struct clk_regmap_mux_data){
588 .shift = 2,
605 .data = &(struct clk_regmap_mux_data){
608 .shift = 16,
619 /* This sub-tree is used a parking clock */
626 .data = &(struct clk_regmap_div_data){
628 .shift = 20,
643 .data = &(struct clk_regmap_mux_data){
646 .shift = 18,
656 /* This sub-tree is used a parking clock */
663 .data = &(struct clk_regmap_mux_data){
666 .shift = 10,
683 .data = &(struct clk_regmap_mux_data){
686 .shift = 11,
705 .data = &(struct clk_regmap_mux_data){
708 .shift = 0,
725 .data = &(struct clk_regmap_mux_data){
728 .shift = 16,
745 .data = &(struct clk_regmap_div_data){
747 .shift = 4,
762 .data = &(struct clk_regmap_mux_data){
765 .shift = 2,
780 .data = &(struct clk_regmap_div_data){
782 .shift = 20,
797 .data = &(struct clk_regmap_mux_data){
800 .shift = 18,
815 .data = &(struct clk_regmap_mux_data){
818 .shift = 10,
833 .data = &(struct clk_regmap_mux_data){
836 .shift = 11,
851 .data = &(struct clk_regmap_mux_data){
854 .shift = 24,
869 .data = &(struct clk_regmap_mux_data){
872 .shift = 25,
887 .data = &(struct clk_regmap_mux_data){
890 .shift = 26,
905 .data = &(struct clk_regmap_mux_data){
908 .shift = 27,
922 unsigned long event, void *data) in g12a_cpu_clk_mux_notifier_cb() argument
947 unsigned long event, void *data) in g12a_cpu_clk_postmux_notifier_cb() argument
958 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
959 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
960 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
961 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
962 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
964 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
965 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
969 clk_hw_set_parent(nb_data->cpu_clk_premux1, in g12a_cpu_clk_postmux_notifier_cb()
970 nb_data->xtal); in g12a_cpu_clk_postmux_notifier_cb()
973 clk_hw_set_parent(nb_data->cpu_clk_postmux1, in g12a_cpu_clk_postmux_notifier_cb()
974 nb_data->cpu_clk_premux1); in g12a_cpu_clk_postmux_notifier_cb()
977 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
978 nb_data->cpu_clk_postmux1); in g12a_cpu_clk_postmux_notifier_cb()
983 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
984 * \- cpu_clk_postmux1 in g12a_cpu_clk_postmux_notifier_cb()
985 * \- cpu_clk_premux1 in g12a_cpu_clk_postmux_notifier_cb()
986 * \- xtal in g12a_cpu_clk_postmux_notifier_cb()
1001 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
1002 nb_data->cpu_clk_postmux0); in g12a_cpu_clk_postmux_notifier_cb()
1007 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
1008 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
1009 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
1010 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1011 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1013 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1014 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1050 unsigned long event, void *data) in g12a_sys_pll_notifier_cb() argument
1061 * \- sys_pll in g12a_sys_pll_notifier_cb()
1062 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1066 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1067 nb_data->cpu_clk_dyn); in g12a_sys_pll_notifier_cb()
1072 * \- cpu_clk_dyn in g12a_sys_pll_notifier_cb()
1073 * \- cpu_clk_dynX in g12a_sys_pll_notifier_cb()
1074 * \- cpu_clk_dynX_sel in g12a_sys_pll_notifier_cb()
1075 * \- cpu_clk_dynX_div in g12a_sys_pll_notifier_cb()
1076 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1077 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1091 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1092 nb_data->sys_pll); in g12a_sys_pll_notifier_cb()
1098 * \- sys_pll in g12a_sys_pll_notifier_cb()
1099 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1133 .data = &(struct clk_regmap_gate_data){
1152 .data = &(struct clk_regmap_gate_data){
1197 .data = &(struct clk_regmap_div_data){
1199 .shift = 3,
1212 .data = &(struct clk_regmap_gate_data){
1231 .data = &(struct clk_regmap_div_data){
1233 .shift = 6,
1246 .data = &(struct clk_regmap_gate_data){
1265 .data = &(struct clk_regmap_div_data){
1267 .shift = 9,
1280 .data = &(struct clk_regmap_gate_data){
1299 .data = &(struct clk_regmap_div_data){
1301 .shift = 20,
1317 .index = -1,
1324 .data = &(struct clk_regmap_gate_data){
1435 .data = &(struct clk_regmap_mux_data){
1438 .shift = 3,
1458 .data = &(struct clk_regmap_gate_data){
1478 .data = &(struct clk_regmap_mux_data){
1481 .shift = 6,
1501 .data = &(struct clk_regmap_gate_data){
1521 .data = &(struct clk_regmap_mux_data){
1524 .shift = 9,
1544 .data = &(struct clk_regmap_gate_data){
1564 .data = &(struct clk_regmap_mux_data){
1567 .shift = 20,
1587 .data = &(struct clk_regmap_gate_data){
1624 .data = &(struct meson_clk_pll_data){
1627 .shift = 28,
1632 .shift = 0,
1637 .shift = 10,
1642 .shift = 0,
1647 .shift = 31,
1652 .shift = 29,
1670 .data = &(struct clk_regmap_div_data){
1672 .shift = 16,
1689 .data = &(struct meson_clk_pll_data){
1692 .shift = 28,
1697 .shift = 0,
1702 .shift = 10,
1707 .shift = 0,
1712 .shift = 31,
1717 .shift = 29,
1734 .data = &(struct clk_regmap_div_data){
1736 .shift = 16,
1764 .data = &(struct meson_clk_pll_data){
1767 .shift = 28,
1772 .shift = 0,
1777 .shift = 10,
1782 .shift = 0,
1787 .shift = 31,
1792 .shift = 29,
1811 .data = &(struct clk_regmap_div_data){
1813 .shift = 16,
1856 .data = &(struct meson_clk_pll_data){
1859 .shift = 28,
1864 .shift = 0,
1869 .shift = 10,
1874 .shift = 0,
1879 .shift = 31,
1884 .shift = 29,
1916 .data = &(struct clk_regmap_div_data){
1918 .shift = 16,
1950 .data = &(struct meson_clk_pll_data){
1953 .shift = 28,
1958 .shift = 0,
1963 .shift = 10,
1968 .shift = 0,
1973 .shift = 30,
1978 .shift = 29,
1998 .data = &(struct clk_regmap_div_data){
2000 .shift = 16,
2016 .data = &(struct clk_regmap_div_data){
2018 .shift = 18,
2034 .data = &(struct clk_regmap_div_data){
2036 .shift = 20,
2063 .data = &(struct clk_regmap_gate_data){
2089 .data = &(struct clk_regmap_gate_data){
2115 .data = &(struct clk_regmap_gate_data){
2143 .data = &(struct clk_regmap_gate_data){
2171 .data = &(struct clk_regmap_mux_data){
2174 .shift = 5,
2205 .data = &(struct meson_clk_mpll_data){
2208 .shift = 0,
2213 .shift = 30,
2218 .shift = 20,
2223 .shift = 29,
2240 .data = &(struct clk_regmap_gate_data){
2258 .data = &(struct meson_clk_mpll_data){
2261 .shift = 0,
2266 .shift = 30,
2271 .shift = 20,
2276 .shift = 29,
2293 .data = &(struct clk_regmap_gate_data){
2311 .data = &(struct meson_clk_mpll_data){
2314 .shift = 0,
2319 .shift = 30,
2324 .shift = 20,
2329 .shift = 29,
2346 .data = &(struct clk_regmap_gate_data){
2364 .data = &(struct meson_clk_mpll_data){
2367 .shift = 0,
2372 .shift = 30,
2377 .shift = 20,
2382 .shift = 29,
2399 .data = &(struct clk_regmap_gate_data){
2424 .data = &(struct clk_regmap_mux_data){
2427 .shift = 12,
2439 .data = &(struct clk_regmap_div_data){
2441 .shift = 0,
2456 .data = &(struct clk_regmap_gate_data){
2487 .data = &(struct clk_regmap_mux_data){
2490 .shift = 9,
2502 .data = &(struct clk_regmap_div_data){
2504 .shift = 0,
2519 .data = &(struct clk_regmap_gate_data){
2536 .data = &(struct clk_regmap_mux_data){
2539 .shift = 25,
2551 .data = &(struct clk_regmap_div_data){
2553 .shift = 16,
2568 .data = &(struct clk_regmap_gate_data){
2585 .data = &(struct clk_regmap_mux_data){
2588 .shift = 9,
2600 .data = &(struct clk_regmap_div_data){
2602 .shift = 0,
2617 .data = &(struct clk_regmap_gate_data){
2635 .data = &(struct meson_vid_pll_div_data){
2638 .shift = 0,
2643 .shift = 16,
2662 .data = &(struct clk_regmap_mux_data){
2665 .shift = 18,
2681 .data = &(struct clk_regmap_gate_data){
2710 .data = &(struct clk_regmap_mux_data){
2713 .shift = 9,
2725 .data = &(struct clk_regmap_div_data){
2727 .shift = 0,
2740 .data = &(struct clk_regmap_gate_data){
2754 .data = &(struct clk_regmap_mux_data){
2757 .shift = 25,
2769 .data = &(struct clk_regmap_div_data){
2771 .shift = 16,
2784 .data = &(struct clk_regmap_gate_data){
2798 .data = &(struct clk_regmap_mux_data){
2801 .shift = 31,
2832 .data = &(struct clk_regmap_mux_data){
2835 .shift = 9,
2848 .data = &(struct clk_regmap_div_data){
2850 .shift = 0,
2866 .data = &(struct clk_regmap_gate_data){
2882 .data = &(struct clk_regmap_mux_data){
2885 .shift = 9,
2898 .data = &(struct clk_regmap_div_data){
2900 .shift = 0,
2916 .data = &(struct clk_regmap_gate_data){
2932 .data = &(struct clk_regmap_mux_data){
2935 .shift = 25,
2948 .data = &(struct clk_regmap_div_data){
2950 .shift = 16,
2966 .data = &(struct clk_regmap_gate_data){
2995 .data = &(struct clk_regmap_mux_data){
2998 .shift = 9,
3010 .data = &(struct clk_regmap_div_data){
3012 .shift = 0,
3027 .data = &(struct clk_regmap_gate_data){
3043 .data = &(struct clk_regmap_mux_data){
3046 .shift = 25,
3058 .data = &(struct clk_regmap_div_data){
3060 .shift = 16,
3075 .data = &(struct clk_regmap_gate_data){
3091 .data = &(struct clk_regmap_mux_data){
3094 .shift = 31,
3113 .data = &(struct clk_regmap_gate_data){
3138 .data = &(struct clk_regmap_mux_data){
3141 .shift = 16,
3153 .data = &(struct clk_regmap_mux_data){
3156 .shift = 16,
3168 .data = &(struct clk_regmap_gate_data){
3182 .data = &(struct clk_regmap_gate_data){
3195 .data = &(struct clk_regmap_div_data){
3197 .shift = 0,
3212 .data = &(struct meson_vclk_div_data){
3215 .shift = 0,
3220 .shift = 16,
3225 .shift = 17,
3242 .data = &(struct clk_regmap_gate_data){
3256 .data = &(struct meson_vclk_gate_data){
3259 .shift = 19,
3264 .shift = 15,
3278 .data = &(struct clk_regmap_gate_data){
3292 .data = &(struct clk_regmap_gate_data){
3306 .data = &(struct clk_regmap_gate_data){
3320 .data = &(struct clk_regmap_gate_data){
3334 .data = &(struct clk_regmap_gate_data){
3348 .data = &(struct clk_regmap_gate_data){
3362 .data = &(struct clk_regmap_gate_data){
3376 .data = &(struct clk_regmap_gate_data){
3390 .data = &(struct clk_regmap_gate_data){
3404 .data = &(struct clk_regmap_gate_data){
3540 .data = &(struct clk_regmap_mux_data){
3543 .shift = 28,
3556 .data = &(struct clk_regmap_mux_data){
3559 .shift = 20,
3572 .data = &(struct clk_regmap_mux_data){
3575 .shift = 12,
3588 .data = &(struct clk_regmap_mux_data){
3591 .shift = 28,
3619 .data = &(struct clk_regmap_mux_data){
3622 .shift = 16,
3635 .data = &(struct clk_regmap_gate_data){
3651 .data = &(struct clk_regmap_gate_data){
3667 .data = &(struct clk_regmap_gate_data){
3683 .data = &(struct clk_regmap_gate_data){
3699 .data = &(struct clk_regmap_gate_data){
3728 .data = &(struct clk_regmap_mux_data){
3731 .shift = 12,
3754 .data = &(struct clk_regmap_div_data){
3756 .shift = 0,
3772 .data = &(struct clk_regmap_gate_data){
3801 .data = &(struct clk_regmap_mux_data){
3804 .shift = 9,
3815 .data = &(struct clk_regmap_div_data){
3817 .shift = 0,
3832 .data = &(struct clk_regmap_gate_data){
3857 .data = &(struct clk_regmap_mux_data){
3860 .shift = 9,
3873 .data = &(struct clk_regmap_div_data){
3875 .shift = 0,
3888 .data = &(struct clk_regmap_gate_data){
3903 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3904 * mux because it does top-to-bottom updates the each clock tree and
3919 .data = &(struct clk_regmap_mux_data){
3922 .shift = 9,
3940 .data = &(struct clk_regmap_div_data){
3942 .shift = 0,
3957 .data = &(struct clk_regmap_gate_data){
3973 .data = &(struct clk_regmap_mux_data){
3976 .shift = 25,
3994 .data = &(struct clk_regmap_div_data){
3996 .shift = 16,
4011 .data = &(struct clk_regmap_gate_data){
4032 .data = &(struct clk_regmap_mux_data){
4035 .shift = 31,
4047 .data = &(struct clk_regmap_div_data){
4049 .shift = 0,
4063 .data = &(struct clk_regmap_gate_data){
4089 .data = &(struct clk_regmap_mux_data){
4092 .shift = 7,
4103 .data = &(struct clk_regmap_div_data){
4105 .shift = 0,
4120 .data = &(struct clk_regmap_gate_data){
4136 .data = &(struct clk_regmap_mux_data){
4139 .shift = 23,
4150 .data = &(struct clk_regmap_div_data){
4152 .shift = 16,
4167 .data = &(struct clk_regmap_gate_data){
4196 .data = &(struct clk_regmap_mux_data){
4199 .shift = 9,
4210 .data = &(struct clk_regmap_div_data){
4212 .shift = 0,
4227 .data = &(struct clk_regmap_gate_data){
4243 .data = &(struct clk_regmap_mux_data){
4246 .shift = 25,
4257 .data = &(struct clk_regmap_div_data){
4259 .shift = 16,
4274 .data = &(struct clk_regmap_gate_data){
5413 struct device *dev = &pdev->dev; in meson_g12b_dvfs_setup()
5490 struct device *dev = &pdev->dev; in meson_g12a_dvfs_setup()
5530 eeclkc_data = of_device_get_match_data(&pdev->dev); in meson_g12a_probe()
5532 return -EINVAL; in meson_g12a_probe()
5541 if (g12a_data->dvfs_setup) in meson_g12a_probe()
5542 return g12a_data->dvfs_setup(pdev); in meson_g12a_probe()
5587 .compatible = "amlogic,g12a-clkc",
5588 .data = &g12a_clkc_data.eeclkc_data
5591 .compatible = "amlogic,g12b-clkc",
5592 .data = &g12b_clkc_data.eeclkc_data
5595 .compatible = "amlogic,sm1-clkc",
5596 .data = &sm1_clkc_data.eeclkc_data
5605 .name = "g12a-clkc",