Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
20 #include "clk-regmap.h"
21 #include "meson-clkc-utils.h"
22 #include "clk-pll.h"
23 #include "clk-mpll.h"
25 #include <dt-bindings/clock/meson8b-clkc.h>
26 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
58 .data = &(struct meson_clk_pll_data){
61 .shift = 30,
66 .shift = 0,
71 .shift = 9,
76 .shift = 0,
81 .shift = 31,
86 .shift = 29,
96 .index = -1,
103 .data = &(struct clk_regmap_div_data){
105 .shift = 16,
131 .index = -1,
140 * Meson8b and Meson8m2. This doubles the input (or output - it's not clear
174 .data = &(struct meson_clk_pll_data){
177 .shift = 30,
182 .shift = 0,
187 .shift = 10,
192 .shift = 0,
197 .shift = 31,
202 .shift = 29,
221 .data = &(struct clk_regmap_div_data){
223 .shift = 16,
239 .data = &(struct clk_regmap_div_data){
241 .shift = 18,
257 .data = &(struct meson_clk_pll_data){
260 .shift = 30,
265 .shift = 0,
270 .shift = 9,
275 .shift = 31,
280 .shift = 29,
291 .index = -1,
298 .data = &(struct clk_regmap_div_data){
300 .shift = 16,
329 .data = &(struct clk_regmap_gate_data){
357 .data = &(struct clk_regmap_gate_data){
385 .data = &(struct clk_regmap_gate_data){
413 .data = &(struct clk_regmap_gate_data){
441 .data = &(struct clk_regmap_gate_data){
456 .data = &(struct clk_regmap_div_data){
458 .shift = 12,
472 .data = &(struct meson_clk_mpll_data){
475 .shift = 0,
480 .shift = 15,
485 .shift = 16,
490 .shift = 25,
505 .data = &(struct clk_regmap_gate_data){
521 .data = &(struct meson_clk_mpll_data){
524 .shift = 0,
529 .shift = 15,
534 .shift = 16,
549 .data = &(struct clk_regmap_gate_data){
565 .data = &(struct meson_clk_mpll_data){
568 .shift = 0,
573 .shift = 15,
578 .shift = 16,
593 .data = &(struct clk_regmap_gate_data){
610 .data = &(struct clk_regmap_mux_data){
613 .shift = 12,
634 .data = &(struct clk_regmap_div_data){
636 .shift = 0,
650 .data = &(struct clk_regmap_gate_data){
666 .data = &(struct clk_regmap_mux_data){
669 .shift = 0,
675 { .fw_name = "xtal", .name = "xtal", .index = -1, },
725 .data = &(struct clk_regmap_div_data){
727 .shift = 20,
745 .data = &(struct clk_regmap_mux_data){
748 .shift = 2,
771 .data = &(struct clk_regmap_mux_data){
774 .shift = 7,
780 { .fw_name = "xtal", .name = "xtal", .index = -1, },
791 .data = &(struct clk_regmap_mux_data){
794 .shift = 9,
806 { .fw_name = "xtal", .name = "xtal", .index = -1, },
814 .data = &(struct clk_regmap_div_data){
816 .shift = 0,
832 .data = &(struct clk_regmap_gate_data){
940 .data = &(struct clk_regmap_mux_data){
943 .shift = 3,
963 .data = &(struct clk_regmap_gate_data){
980 .data = &(struct clk_regmap_mux_data){
983 .shift = 6,
1002 .data = &(struct clk_regmap_gate_data){
1020 .data = &(struct clk_regmap_mux_data){
1023 .shift = 9,
1043 .data = &(struct clk_regmap_gate_data){
1060 .data = &(struct clk_regmap_mux_data){
1063 .shift = 12,
1082 .data = &(struct clk_regmap_gate_data){
1100 .data = &(struct clk_regmap_gate_data){
1116 .data = &(struct clk_regmap_mux_data){
1119 .shift = 15,
1139 .data = &(struct clk_regmap_gate_data){
1155 .data = &(struct clk_regmap_div_data){
1157 .shift = 4,
1172 .data = &(struct clk_regmap_div_data){
1174 .shift = 12,
1189 .data = &(struct clk_regmap_mux_data){
1192 .shift = 8,
1208 .data = &(struct clk_regmap_div_data){
1210 .shift = 0,
1235 .data = &(struct clk_regmap_mux_data){
1238 .shift = 16,
1250 .data = &(struct clk_regmap_gate_data){
1266 .data = &(struct clk_regmap_gate_data){
1282 .data = &(struct clk_regmap_gate_data){
1312 .data = &(struct clk_regmap_gate_data){
1342 .data = &(struct clk_regmap_gate_data){
1372 .data = &(struct clk_regmap_gate_data){
1402 .data = &(struct clk_regmap_gate_data){
1418 .data = &(struct clk_regmap_mux_data){
1421 .shift = 16,
1433 .data = &(struct clk_regmap_gate_data){
1449 .data = &(struct clk_regmap_gate_data){
1465 .data = &(struct clk_regmap_gate_data){
1495 .data = &(struct clk_regmap_gate_data){
1525 .data = &(struct clk_regmap_gate_data){
1555 .data = &(struct clk_regmap_gate_data){
1585 .data = &(struct clk_regmap_gate_data){
1609 .data = &(struct clk_regmap_mux_data){
1612 .shift = 20,
1624 .data = &(struct clk_regmap_gate_data){
1640 .data = &(struct clk_regmap_mux_data){
1643 .shift = 24,
1655 .data = &(struct clk_regmap_gate_data){
1671 .data = &(struct clk_regmap_mux_data){
1674 .shift = 28,
1686 .data = &(struct clk_regmap_gate_data){
1702 .data = &(struct clk_regmap_mux_data){
1705 .shift = 16,
1717 .data = &(struct clk_regmap_gate_data){
1741 .data = &(struct clk_regmap_mux_data){
1744 .shift = 12,
1756 .data = &(struct clk_regmap_gate_data){
1772 .data = &(struct clk_regmap_mux_data){
1775 .shift = 28,
1787 .data = &(struct clk_regmap_gate_data){
1803 .data = &(struct clk_regmap_mux_data){
1806 .shift = 9,
1816 .index = -1,
1824 .data = &(struct clk_regmap_div_data){
1826 .shift = 0,
1841 .data = &(struct clk_regmap_gate_data){
1858 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
1859 * actually manage this glitch-free mux because it does top-to-bottom
1862 * Meson8 only has mali_0 and no glitch-free mux.
1865 { .fw_name = "xtal", .name = "xtal", .index = -1, },
1877 .data = &(struct clk_regmap_mux_data){
1880 .shift = 9,
1899 .data = &(struct clk_regmap_div_data){
1901 .shift = 0,
1916 .data = &(struct clk_regmap_gate_data){
1932 .data = &(struct clk_regmap_mux_data){
1935 .shift = 25,
1954 .data = &(struct clk_regmap_div_data){
1956 .shift = 16,
1971 .data = &(struct clk_regmap_gate_data){
1987 .data = &(struct clk_regmap_mux_data){
1990 .shift = 31,
2017 .data = &(struct meson_clk_pll_data){
2020 .shift = 30,
2025 .shift = 0,
2030 .shift = 9,
2035 .shift = 31,
2040 .shift = 29,
2053 .index = -1,
2060 .data = &(struct clk_regmap_div_data){
2062 .shift = 16,
2092 .data = &(struct clk_regmap_mux_data){
2095 .shift = 9,
2107 .data = &(struct clk_regmap_mux_data){
2110 .shift = 9,
2122 .data = &(struct clk_regmap_div_data){
2124 .shift = 0,
2139 .index = -1,
2147 .data = &(struct clk_regmap_gate_data){
2163 .data = &(struct clk_regmap_mux_data){
2166 .shift = 25,
2178 .data = &(struct clk_regmap_mux_data){
2181 .shift = 25,
2193 .data = &(struct clk_regmap_div_data){
2195 .shift = 16,
2210 .index = -1,
2218 .data = &(struct clk_regmap_gate_data){
2235 * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
2236 * actually manage this glitch-free mux because it does top-to-bottom
2239 * Meson8 only has vpu_0 and no glitch-free mux.
2242 .data = &(struct clk_regmap_mux_data){
2245 .shift = 31,
2269 .data = &(struct clk_regmap_mux_data){
2272 .shift = 9,
2285 .data = &(struct clk_regmap_div_data){
2287 .shift = 0,
2303 .data = &(struct clk_regmap_gate_data){
2319 .data = &(struct clk_regmap_div_data){
2321 .shift = 0,
2337 .data = &(struct clk_regmap_gate_data){
2353 .data = &(struct clk_regmap_mux_data){
2356 .shift = 15,
2372 .data = &(struct clk_regmap_mux_data){
2375 .shift = 25,
2388 .data = &(struct clk_regmap_div_data){
2390 .shift = 16,
2406 .data = &(struct clk_regmap_gate_data){
2422 .data = &(struct clk_regmap_mux_data){
2425 .shift = 9,
2438 .data = &(struct clk_regmap_div_data){
2440 .shift = 0,
2456 .data = &(struct clk_regmap_gate_data){
2472 .data = &(struct clk_regmap_mux_data){
2475 .shift = 25,
2488 .data = &(struct clk_regmap_div_data){
2490 .shift = 16,
2506 .data = &(struct clk_regmap_gate_data){
2522 .data = &(struct clk_regmap_mux_data){
2525 .shift = 31,
2550 .data = &(struct clk_regmap_mux_data){
2553 .shift = 9,
2566 .data = &(struct clk_regmap_div_data) {
2568 .shift = 0,
2584 .data = &(struct clk_regmap_gate_data){
2609 .data = &(struct clk_regmap_mux_data){
2612 .shift = 25,
2625 .data = &(struct clk_regmap_div_data){
2627 .shift = 16,
2643 .data = &(struct clk_regmap_gate_data){
2659 .data = &(struct clk_regmap_mux_data){
2662 .shift = 27,
2673 * The parent is specific to origin of the audio data. Let the
3702 return -EINVAL; in meson8b_clk_reset_update()
3706 if (assert != reset->active_low) in meson8b_clk_reset_update()
3707 value = BIT(reset->bit_idx); in meson8b_clk_reset_update()
3709 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, in meson8b_clk_reset_update()
3710 BIT(reset->bit_idx), value); in meson8b_clk_reset_update()
3738 unsigned long event, void *data) in meson8b_cpu_clk_notifier_cb() argument
3748 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0); in meson8b_cpu_clk_notifier_cb()
3753 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1); in meson8b_cpu_clk_notifier_cb()
3760 ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk); in meson8b_cpu_clk_notifier_cb()
3802 pr_err("failed to get HHI regmap - Trying obsolete regs\n"); in meson8b_clkc_init_common()
3811 rstc->regmap = map; in meson8b_clkc_init_common()
3812 rstc->reset.ops = &meson8b_clk_reset_ops; in meson8b_clkc_init_common()
3813 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits); in meson8b_clkc_init_common()
3814 rstc->reset.of_node = np; in meson8b_clkc_init_common()
3815 ret = reset_controller_register(&rstc->reset); in meson8b_clkc_init_common()
3824 meson8b_clk_regmaps[i]->map = map; in meson8b_clkc_init_common()
3830 for (i = CLKID_PLL_FIXED; i < hw_clks->num; i++) { in meson8b_clkc_init_common()
3832 if (!hw_clks->hws[i]) in meson8b_clkc_init_common()
3835 ret = of_clk_hw_register(np, hw_clks->hws[i]); in meson8b_clkc_init_common()
3840 meson8b_cpu_nb_data.cpu_clk = hw_clks->hws[CLKID_CPUCLK]; in meson8b_clkc_init_common()
3876 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3878 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3880 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",