Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
9 #include <linux/clk-provider.h>
13 #include "clk-mpll.h"
14 #include "clk-pll.h"
15 #include "clk-regmap.h"
16 #include "s4-pll.h"
17 #include "meson-clkc-utils.h"
18 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
23 * in the kernel phase. Write of fixed PLL-related register will cause the system to crash.
28 .data = &(struct meson_clk_pll_data){
31 .shift = 28,
36 .shift = 0,
41 .shift = 0,
46 .shift = 10,
51 .shift = 31,
56 .shift = 29,
71 .data = &(struct clk_regmap_div_data){
73 .shift = 16,
103 .data = &(struct clk_regmap_gate_data){
129 .data = &(struct clk_regmap_gate_data){
155 .data = &(struct clk_regmap_gate_data){
181 .data = &(struct clk_regmap_gate_data){
207 .data = &(struct clk_regmap_gate_data){
235 .data = &(struct clk_regmap_gate_data){
267 .data = &(struct meson_clk_pll_data){
270 .shift = 28,
275 .shift = 0,
280 .shift = 10,
285 .shift = 31,
290 .shift = 29,
308 .data = &(struct clk_regmap_div_data){
310 .shift = 16,
338 .data = &(struct meson_clk_pll_data){
341 .shift = 28,
346 .shift = 0,
351 .shift = 10,
356 .shift = 0,
361 .shift = 31,
366 .shift = 29,
386 .data = &(struct clk_regmap_div_data){
388 .shift = 16,
405 .data = &(struct meson_clk_pll_data){
408 .shift = 28,
413 .shift = 0,
418 .shift = 10,
423 .shift = 31,
428 .shift = 29,
444 .data = &(struct clk_regmap_div_data){
446 .shift = 16,
462 .data = &(struct clk_regmap_div_data){
464 .shift = 20,
493 .data = &(struct clk_regmap_mux_data){
496 .shift = 5,
527 .data = &(struct meson_clk_mpll_data){
530 .shift = 0,
535 .shift = 30,
540 .shift = 20,
545 .shift = 29,
562 .data = &(struct clk_regmap_gate_data){
580 .data = &(struct meson_clk_mpll_data){
583 .shift = 0,
588 .shift = 30,
593 .shift = 20,
598 .shift = 29,
615 .data = &(struct clk_regmap_gate_data){
633 .data = &(struct meson_clk_mpll_data){
636 .shift = 0,
641 .shift = 30,
646 .shift = 20,
651 .shift = 29,
668 .data = &(struct clk_regmap_gate_data){
686 .data = &(struct meson_clk_mpll_data){
689 .shift = 0,
694 .shift = 30,
699 .shift = 20,
704 .shift = 29,
721 .data = &(struct clk_regmap_gate_data){
815 struct device *dev = &pdev->dev; in meson_s4_pll_probe()
837 s4_pll_clk_regmaps[i]->map = regmap; in meson_s4_pll_probe()
857 .compatible = "amlogic,s4-pll-clkc",
866 .name = "s4-pll-clkc",