Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
24 #include <dt-bindings/clock/axg-clkc.h>
27 .data = &(struct meson_clk_pll_data){
30 .shift = 30,
35 .shift = 0,
40 .shift = 9,
45 .shift = 0,
50 .shift = 31,
55 .shift = 29,
70 .data = &(struct clk_regmap_div_data){
72 .shift = 16,
91 .data = &(struct meson_clk_pll_data){
94 .shift = 30,
99 .shift = 0,
104 .shift = 9,
109 .shift = 31,
114 .shift = 29,
129 .data = &(struct clk_regmap_div_data){
131 .shift = 16,
188 .data = &(struct meson_clk_pll_data){
191 .shift = 30,
196 .shift = 0,
201 .shift = 9,
206 .shift = 0,
211 .shift = 31,
216 .shift = 29,
234 .data = &(struct clk_regmap_div_data){
236 .shift = 16,
260 .data = &(struct meson_clk_pll_data){
263 .shift = 30,
268 .shift = 0,
273 .shift = 9,
278 .shift = 0,
283 .shift = 31,
288 .shift = 29,
307 .data = &(struct clk_regmap_div_data){
309 .shift = 16,
336 .data = &(struct clk_regmap_gate_data){
363 .data = &(struct clk_regmap_gate_data){
382 * b) CCF has a clock hand-off mechanism to make the sure the
401 .data = &(struct clk_regmap_gate_data){
427 .data = &(struct clk_regmap_gate_data){
455 .data = &(struct clk_regmap_gate_data){
470 .data = &(struct clk_regmap_div_data){
472 .shift = 12,
486 .data = &(struct meson_clk_mpll_data){
489 .shift = 0,
494 .shift = 15,
499 .shift = 16,
504 .shift = 0,
520 .data = &(struct clk_regmap_gate_data){
536 .data = &(struct meson_clk_mpll_data){
539 .shift = 0,
544 .shift = 15,
549 .shift = 16,
554 .shift = 1,
570 .data = &(struct clk_regmap_gate_data){
586 .data = &(struct meson_clk_mpll_data){
589 .shift = 0,
594 .shift = 15,
599 .shift = 16,
604 .shift = 25,
609 .shift = 2,
625 .data = &(struct clk_regmap_gate_data){
641 .data = &(struct meson_clk_mpll_data){
644 .shift = 12,
649 .shift = 11,
654 .shift = 2,
659 .shift = 3,
675 .data = &(struct clk_regmap_gate_data){
709 .data = &(struct meson_clk_pll_data){
712 .shift = 30,
717 .shift = 0,
722 .shift = 9,
727 .shift = 0,
732 .shift = 31,
737 .shift = 29,
755 .data = &(struct clk_regmap_div_data){
757 .shift = 16,
773 .data = &(struct clk_regmap_div_data){
775 .shift = 6,
791 .data = &(struct clk_regmap_mux_data){
794 .shift = 2,
808 .data = &(struct clk_regmap_mux_data){
811 .shift = 1,
825 .data = &(struct clk_regmap_gate_data){
840 .data = &(struct clk_regmap_gate_data){
865 .data = &(struct clk_regmap_mux_data){
868 .shift = 12,
880 .data = &(struct clk_regmap_div_data){
882 .shift = 0,
897 .data = &(struct clk_regmap_gate_data){
928 .data = &(struct clk_regmap_mux_data){
931 .shift = 25,
943 .data = &(struct clk_regmap_div_data){
945 .shift = 16,
961 .data = &(struct clk_regmap_gate_data){
978 .data = &(struct clk_regmap_mux_data){
981 .shift = 9,
993 .data = &(struct clk_regmap_div_data){
995 .shift = 0,
1011 .data = &(struct clk_regmap_gate_data){
1036 .data = &(struct clk_regmap_mux_data){
1039 .shift = 9,
1052 .data = &(struct clk_regmap_div_data){
1054 .shift = 0,
1067 .data = &(struct clk_regmap_gate_data){
1085 .data = &(struct clk_regmap_mux_data){
1088 .shift = 25,
1101 .data = &(struct clk_regmap_div_data){
1103 .shift = 16,
1116 .data = &(struct clk_regmap_gate_data){
1134 .data = &(struct clk_regmap_mux_data){
1137 .shift = 31,
1154 .data = &(struct clk_regmap_mux_data){
1157 .shift = 9,
1169 .data = &(struct clk_regmap_div_data){
1171 .shift = 0,
1186 .data = &(struct clk_regmap_gate_data){
1202 .data = &(struct clk_regmap_mux_data){
1205 .shift = 25,
1217 .data = &(struct clk_regmap_div_data){
1219 .shift = 16,
1234 .data = &(struct clk_regmap_gate_data){
1250 .data = &(struct clk_regmap_mux_data){
1253 .shift = 31,
1268 .data = &(struct clk_regmap_gate_data){
1294 .data = &(struct clk_regmap_mux_data){
1297 .shift = 16,
1309 .data = &(struct clk_regmap_mux_data){
1312 .shift = 16,
1324 .data = &(struct clk_regmap_gate_data){
1338 .data = &(struct clk_regmap_gate_data){
1352 .data = &(struct clk_regmap_div_data){
1354 .shift = 0,
1369 .data = &(struct clk_regmap_div_data){
1371 .shift = 0,
1386 .data = &(struct clk_regmap_gate_data){
1400 .data = &(struct clk_regmap_gate_data){
1414 .data = &(struct clk_regmap_gate_data){
1428 .data = &(struct clk_regmap_gate_data){
1442 .data = &(struct clk_regmap_gate_data){
1456 .data = &(struct clk_regmap_gate_data){
1470 .data = &(struct clk_regmap_gate_data){
1484 .data = &(struct clk_regmap_gate_data){
1498 .data = &(struct clk_regmap_gate_data){
1512 .data = &(struct clk_regmap_gate_data){
1526 .data = &(struct clk_regmap_gate_data){
1540 .data = &(struct clk_regmap_gate_data){
1672 .data = &(struct clk_regmap_mux_data){
1675 .shift = 12,
1688 .data = &(struct clk_regmap_gate_data){
1716 .data = &(struct clk_regmap_mux_data){
1719 .shift = 21,
1733 .data = &(struct clk_regmap_div_data){
1735 .shift = 12,
1749 .data = &(struct clk_regmap_gate_data){
1780 .data = &(struct clk_regmap_mux_data){
1783 .shift = 12,
1801 .data = &(struct clk_regmap_div_data){
1803 .shift = 0,
1818 .data = &(struct clk_regmap_gate_data){
2168 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2176 .name = "axg-clkc",