Home
last modified time | relevance | path

Searched +full:cycle +full:- +full:3 (Results 1 – 25 of 1061) sorted by relevance

12345678910>>...43

/freebsd/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
15 "Counter": "0,1,2,3",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3",
46 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/ivytown/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
15 "Counter": "0,1,2,3",
16 "CounterHTOff": "0,1,2,3,4,5,6,7",
25 "Counter": "0,1,2,3",
26 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3",
36 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3",
46 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/share/doc/psd/18.gprof/
H A Dpostp.me12 .\" 3. Neither the name of the University nor the names of its contributors
88 In these cases, we discover strongly-connected
92 We use a variation of Tarjan's strongly-connected
94 that discovers strongly-connected components as it is assigning
99 For example, a self-recursive routine
100 (a trivial cycle in the call graph)
109 Time is not propagated from one member of a cycle to another,
112 In addition, children of one member of a cycle
113 must be considered children of all members of the cycle.
114 Similarly, parents of one member of the cycle must inherit
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td1 //===- P9InstrResources.td - P9 Instruction Resource Defs -*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // - Each CPU is made up of two superslices.
17 // - Each superslice is made up of two slices. Therefore, there are 4 slices
19 // - Up to 6 instructions can be dispatched to each CPU. Three per superslice.
20 // - Each CPU has:
21 // - One CY (Crypto) unit P9_CY_*
22 // - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_*
23 // - Two PM (Permute) units. One on each superslice. P9_PM_*
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Dpipeline.json5 "Counter": "0,1,2,3",
9 "PEBScounters": "0,1,2,3",
16 "Counter": "0,1,2,3",
20 "PEBScounters": "0,1,2,3",
27 "Counter": "0,1,2,3",
31 "PEBScounters": "0,1,2,3",
38 "Counter": "0,1,2,3",
42 "PEBScounters": "0,1,2,3",
49 "Counter": "0,1,2,3",
53 "PEBScounters": "0,1,2,3",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A Dpipeline.json5 "Counter": "0,1,2,3",
9 "PEBScounters": "0,1,2,3",
16 "Counter": "0,1,2,3",
20 "PEBScounters": "0,1,2,3",
27 "Counter": "0,1,2,3",
31 "PEBScounters": "0,1,2,3",
38 "Counter": "0,1,2,3",
42 "PEBScounters": "0,1,2,3",
49 "Counter": "0,1,2,3",
53 "PEBScounters": "0,1,2,3",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/jaketown/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A Dfloating-point.json4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3",
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3",
24 "CounterHTOff": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3",
33 "CounterHTOff": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3",
42 "CounterHTOff": "0,1,2,3,4,5,6,7",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A Dfloating-point.json6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
12 "BriefDescription": "Total number uOps assigned to pipe 3.",
13 …-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric op…
20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t…
40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e…
46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num…
52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary …
[all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Dpwm-vibrator.txt4 strength increases based on the duty cycle of the enable PWM channel
5 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
8 driven at fixed duty cycle. If available this is can be used to increase
12 - compatible: should contain "pwm-vibrator"
13 - pwm-names: Should contain "enable" and optionally "direction"
14 - pwms: Should contain a PWM handle for each entry in pwm-names
17 - vcc-supply: Phandle for the regulator supplying power
18 - direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
26 pinctrl-single,pins = <
32 pinctrl-single,pins = <
[all …]
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Drenesas,sh-msiof.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
22 - items:
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A Dvirtual-memory.json5 "Counter": "0,1,2,3",
9 "PEBScounters": "0,1,2,3",
17 "Counter": "0,1,2,3",
21 "PEBScounters": "0,1,2,3",
29 "Counter": "0,1,2,3",
33 "PEBScounters": "0,1,2,3",
39 "BriefDescription": "Page walks outstanding due to a demand load every cycle.",
41 "Counter": "0,1,2,3",
45 "PEBScounters": "0,1,2,3",
46 …"PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand dat…
[all …]
/freebsd/lib/libpmc/
H A Dpmc.haswellxeon.346 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
56 .Xr pmc_cpuinfo 3 .
60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
62 .%N "Order Number: 325462-052US"
68 .Xr pmc.iaf 3 .
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
90 Configure the Off-core Response bits.
[all …]
H A Dpmc.haswell.345 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
55 .Xr pmc_cpuinfo 3 .
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
61 .%N "Order Number: 325462-045US"
67 .Xr pmc.iaf 3 .
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
[all …]
H A Dpmc.sandybridge.341 CPUs contain PMCs conforming to the version 3 of the
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
53 .Xr pmc.tsc 3 .
58 .Xr pmc_cpuinfo 3 .
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
63 .%T "Volume 3B: System Programming Guide, Part 2"
64 .%N "Order Number: 253669-039US"
70 .Xr pmc.iaf 3 .
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
[all …]
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DTimelineView.h1 //===--------------------- TimelineView.h -----------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file implements a timeline view for the llvm-mca tool.
24 /// [0,3] .DeeeER . .. vaddss %xmm1, %xmm0, %xmm3
28 /// [1,0] . DeE------R .. vmovshdup %xmm0, %xmm1
29 /// [1,1] . DeE------R .. vpermilpd $1, %xmm0, %xmm2
30 /// [1,2] . DeE-----R .. vpermilps $231, %xmm0, %xmm5
31 /// [1,3] . D=eeeE--R .. vaddss %xmm1, %xmm0, %xmm3
41 /// column is the information related to a specific cycle of execution.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DWindowScheduler.cpp1 //======----------- WindowScheduler.cpp - window scheduler -------------======//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
30 // target-specific logic can be added in initialize(), preProcess(), and
37 //===----------------------------------------------------------------------===//
64 WindowSearchNum("window-search-num",
70 "window-search-ratio",
77 "window-ii-coeff",
83 "window-region-limit",
86 cl::Hidden, cl::init(3));
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A Dbasic.json6 "PublicDescription": "Cycle Count"
18 "PublicDescription": "Level-1 I-Cache Directory Write Count"
21 "EventCode": "3",
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
30 "PublicDescription": "Level-1 D-Cache Directory Write Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41 "BriefDescription": "Problem-State CPU Cycles",
42 "PublicDescription": "Problem-State Cycle Count"
47 "BriefDescription": "Problem-State Instructions",
48 "PublicDescription": "Problem-State Instruction Count"
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A Dbasic.json6 "PublicDescription": "Cycle Count"
18 "PublicDescription": "Level-1 I-Cache Directory Write Count"
21 "EventCode": "3",
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
30 "PublicDescription": "Level-1 D-Cache Directory Write Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41 "BriefDescription": "Problem-State CPU Cycles",
42 "PublicDescription": "Problem-State Cycle Count"
47 "BriefDescription": "Problem-State Instructions",
48 "PublicDescription": "Problem-State Instruction Count"
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A Dbasic.json6 "PublicDescription": "Cycle Count"
18 "PublicDescription": "Level-1 I-Cache Directory Write Count"
21 "EventCode": "3",
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
30 "PublicDescription": "Level-1 D-Cache Directory Write Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41 "BriefDescription": "Problem-State CPU Cycles",
42 "PublicDescription": "Problem-State Cycle Count"
47 "BriefDescription": "Problem-State Instructions",
48 "PublicDescription": "Problem-State Instruction Count"
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A Dbasic.json6 "PublicDescription": "Cycle Count"
18 "PublicDescription": "Level-1 I-Cache Directory Write Count"
21 "EventCode": "3",
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
30 "PublicDescription": "Level-1 D-Cache Directory Write Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41 "BriefDescription": "Problem-State CPU Cycles",
42 "PublicDescription": "Problem-State Cycle Count"
47 "BriefDescription": "Problem-State Instructions",
48 "PublicDescription": "Problem-State Instruction Count"
[all …]
/freebsd/usr.bin/clang/llvm-mca/
H A Dllvm-mca.14 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
19 . nr rst2man-indent-level +1
[all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A Dextended.json5 "BriefDescription": "L1D Read-only Exclusive Writes",
6 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
18 …cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle"
23 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
24 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
29 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
36 …on": "A directory write to the Level-1 Data cache directory where the returned cache line was sour…
48 …e. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle"
54 … "A directory write to the Level-1 Instruction cache directory where the returned cache line was s…
[all …]

12345678910>>...43