Lines Matching +full:cycle +full:- +full:3

46 .Bl -tag -width "Li PMC_CLASS_IAP"
48 Fixed-function counters that count only one hardware event per counter.
56 .Xr pmc_cpuinfo 3 .
60 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
61 .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
62 .%N "Order Number: 325462-052US"
68 .Xr pmc.iaf 3 .
71 .Bl -column "PMC_CAP_INTERRUPT" "Support"
88 .Bl -tag -width indent
90 Configure the Off-core Response bits.
91 .Bl -tag -width indent
129 M-state initial lookup stat in L3.
131 E-state.
133 S-state.
135 F-state.
139 No details on snoop-related information.
149 Hit denotes a cache-line was valid before snoop effect.
160 A snoop was needed and it HitM-ed in local or remote cache.
161 HitM denotes a cache-line was in modified state before effect as a results of snoop.
167 Target was non-DRAM system address.
172 events measured in a cycle is greater than or equal to
175 Configure the PMC to count the number of de-asserted to asserted
184 events per cycle is less than the value specified by the
192 or 3.
202 .Bl -tag -width indent
209 Speculative cache-line split load uops dispatched to
213 Speculative cache-line split Store-address uops
237 Cycle PMH is busy with a walk.
250 DTLB demand load misses with low part of linear-to-
259 ncrements each cycle the # of Uops issued by the
265 Number of flags-merge uops allocated.
270 Such uop has 3 sources (e.g. 2 sources + immediate)
325 .Pq Event 24H , Umask 3FH
342 .Pq Event 3CH , Umask 00H
349 .Pq Event 3CH , Umask 01H
355 every cycle.
388 DTLB store misses with low part of linear-to-physical
392 Non-SW-prefetch load dispatches that hit fill buffer
396 Non-SW-prefetch load dispatches that hit fill buffer
457 Increment each cycle # of uops delivered to IDQ from
462 Increment each cycle. # of uops delivered to IDQ
467 Increment each cycle # of uops delivered to IDQ
473 ncrement each cycle # of uops delivered to IDQ
478 Increment each cycle # of uops delivered to IDQ from
498 .Pq Event 79H , Umask 3CH
522 Cycle PMH is busy with a walk.
596 Count number of non-delivered uops to RAT per
612 Cycles which a Uop is dispatched on port 3 in this
643 Cycles stalled due to re-order buffer full.
647 Set Cmask=2 to count cycle.
651 Set Cmask=2 to count cycle.
658 Set Cmask=8 to count cycle.
678 Counts total number of uops to be executed per-core
679 each cycle.
714 DTLB flush attempts of the thread-specific entries.
727 Number of transitions from AVX-256 to legacy SSE
731 Number of transitions from SSE to AVX-256 when
739 Counts the number of micro-ops retired, Use
745 cycle.
752 Number of self-modifying-code machine clears
858 and cross-core snoop missed in on-pkg core cache.
862 cross-core snoop hits in on-pkg core cache.
877 Number of front end re-steers due to BPU
924 .Xr pmc 3 ,
925 .Xr pmc.amd 3 ,
926 .Xr pmc.atom 3 ,
927 .Xr pmc.core 3 ,
928 .Xr pmc.corei7 3 ,
929 .Xr pmc.corei7uc 3 ,
930 .Xr pmc.haswell 3 ,
931 .Xr pmc.haswelluc 3 ,
932 .Xr pmc.iaf 3 ,
933 .Xr pmc.ivybridge 3 ,
934 .Xr pmc.ivybridgexeon 3 ,
935 .Xr pmc.sandybridge 3 ,
936 .Xr pmc.sandybridgeuc 3 ,
937 .Xr pmc.sandybridgexeon 3 ,
938 .Xr pmc.soft 3 ,
939 .Xr pmc.tsc 3 ,
940 .Xr pmc.ucf 3 ,
941 .Xr pmc.westmere 3 ,
942 .Xr pmc.westmereuc 3 ,
943 .Xr pmc_cpuinfo 3 ,
944 .Xr pmclog 3 ,