Lines Matching +full:cycle +full:- +full:3

45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
55 .Xr pmc_cpuinfo 3 .
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
60 .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
61 .%N "Order Number: 325462-045US"
67 .Xr pmc.iaf 3 .
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
128 M-state initial lookup stat in L3.
130 E-state.
132 S-state.
134 F-state.
138 No details on snoop-related information.
148 Hit denotes a cache-line was valid before snoop effect.
159 A snoop was needed and it HitM-ed in local or remote cache.
160 HitM denotes a cache-line was in modified state before effect as a results of snoop.
166 Target was non-DRAM system address.
171 events measured in a cycle is greater than or equal to
174 Configure the PMC to count the number of de-asserted to asserted
183 events per cycle is less than the value specified by the
191 or 3.
201 .Bl -tag -width indent
208 Speculative cache-line split load uops dispatched to
212 Speculative cache-line split Store-address uops
236 Cycle PMH is busy with a walk.
249 DTLB demand load misses with low part of linear-to-
258 ncrements each cycle the # of Uops issued by the
264 Number of flags-merge uops allocated.
269 Such uop has 3 sources (e.g. 2 sources + immediate)
324 .Pq Event 24H , Umask 3FH
341 .Pq Event 3CH , Umask 00H
346 .Pq Event 3CH , Umask 01H
351 Increments the number of outstanding L1D misses every cycle.
384 DTLB store misses with low part of linear-to-physical
388 Non-SW-prefetch load dispatches that hit fill buffer
392 Non-SW-prefetch load dispatches that hit fill buffer
449 Increment each cycle # of uops delivered to IDQ from MITE path.
453 Increment each cycle. # of uops delivered to IDQ
458 Increment each cycle # of uops delivered to IDQ when MS_busy by DSB.
463 ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE.
467 Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE.
486 .Pq Event 79H , Umask 3CH
509 Cycle PMH is busy with a walk.
583 Count number of non-delivered uops to RAT per
599 Cycles which a Uop is dispatched on port 3 in this
630 Cycles stalled due to re-order buffer full.
634 Set Cmask=2 to count cycle.
638 Set Cmask=2 to count cycle.
645 Set Cmask=8 to count cycle.
666 Counts total number of uops to be executed per-core
667 each cycle.
702 DTLB flush attempts of the thread-specific entries.
715 Number of transitions from AVX-256 to legacy SSE
719 Number of transitions from SSE to AVX-256 when
727 Counts the number of micro-ops retired, Use
733 cycle.
740 Number of self-modifying-code machine clears
845 and cross-core snoop missed in on-pkg core cache.
849 cross-core snoop hits in on-pkg core cache.
864 Number of front end re-steers due to BPU
911 .Xr pmc 3 ,
912 .Xr pmc.amd 3 ,
913 .Xr pmc.atom 3 ,
914 .Xr pmc.core 3 ,
915 .Xr pmc.corei7 3 ,
916 .Xr pmc.corei7uc 3 ,
917 .Xr pmc.haswelluc 3 ,
918 .Xr pmc.iaf 3 ,
919 .Xr pmc.ivybridge 3 ,
920 .Xr pmc.ivybridgexeon 3 ,
921 .Xr pmc.sandybridge 3 ,
922 .Xr pmc.sandybridgeuc 3 ,
923 .Xr pmc.sandybridgexeon 3 ,
924 .Xr pmc.soft 3 ,
925 .Xr pmc.tsc 3 ,
926 .Xr pmc.ucf 3 ,
927 .Xr pmc.westmere 3 ,
928 .Xr pmc.westmereuc 3 ,
929 .Xr pmc_cpuinfo 3 ,
930 .Xr pmclog 3 ,
938 .An -nosplit