Lines Matching +full:cycle +full:- +full:3

41 CPUs contain PMCs conforming to the version 3 of the
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
53 .Xr pmc.tsc 3 .
58 .Xr pmc_cpuinfo 3 .
62 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
63 .%T "Volume 3B: System Programming Guide, Part 2"
64 .%N "Order Number: 253669-039US"
70 .Xr pmc.iaf 3 .
73 .Bl -column "PMC_CAP_INTERRUPT" "Support"
90 .Bl -tag -width indent
92 Configure the Off-core Response bits.
93 .Bl -tag -width indent
130 M-state initial lookup stat in L3.
132 E-state.
134 S-state.
136 F-state.
140 No details on snoop-related information.
150 Hit denotes a cache-line was valid before snoop effect.
161 A snoop was needed and it HitM-ed in local or remote cache.
162 HitM denotes a cache-line was in modified state before effect as a results of snoop.
168 Target was non-DRAM system address.
173 events measured in a cycle is greater than or equal to
176 Configure the PMC to count the number of de-asserted to asserted
185 events per cycle is less than the value specified by the
193 or 3.
203 .Bl -tag -width indent
218 Speculative cache-line split load uops dispatched to L1D.
221 Speculative cache-line split Store-address uops dispatched to L1D.
238 Cycle PMH is busy with a walk.
253 Increments each cycle the # of Uops issued by the RAT to RS.
273 Counts 256-bit packed single-precision floating-point instructions.
276 Counts 256-bit packed double-precision floating-point instructions.
283 Counts the number of instructions written into the IQ every cycle.
344 .Pq Event 3CH, Umask 00H
350 .Pq Event 3CH, Umask 01H
354 Increments the number of outstanding L1D misses every cycle.
373 Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.
376 Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.
382 This accounts for both L1 streamer and IP-based (IPP) HW prefetchers.
399 Increments the number of flags-merge uops in flight each cycle.
452 Increment each cycle # of uops delivered to IDQ from MITE path.
457 Increment each cycle.
463 Increment each cycle # of uops delivered to IDQ when MS busy by DSB.
469 Increment each cycle # of uops delivered to IDQ when MS is busy by MITE.
474 Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE.
489 Cycle PMH is busy with a walk.
556 Count number of non-delivered uops to RAT per thread.
575 Cycles which a load uop is dispatched on port 3.
578 Cycles which a store address uop is dispatched on port 3.
581 .Pq Cycles which a Uop is dispatched on port 3.
603 Cycles stalled due to re-order buffer full.
625 DSB Fill encountered > 3 DSB lines.
644 Counts total number of uops to be dispatched per-thread each cycle.
648 Counts total number of uops to be dispatched per-core each cycle.
656 of the format [base + offset], 2. the offset is between 1 and 2047, 3. the
661 Off-core Response Performance Monitoring; PMC0 only.
665 Off-core Response Performance Monitoring.
670 DTLB flush attempts of the thread-specific entries.
694 Number of assists associated with 256-bit AVX store operations.
700 Number of transitions from SSE to AVX-256 when penalty applicable.
703 Counts the number of micro-ops retired.
707 Counts the number of retirement slots used each cycle.
828 Retired load uops which data sources were LLC hit and cross-core snoop missed in
829 on-pkg core cache.
832 Retired load uops which data sources were LLC and cross-core snoop hits in
833 on-pkg core cache.
879 .It Li L2_LINES-IN.ALL
904 .Xr pmc 3 ,
905 .Xr pmc.amd 3 ,
906 .Xr pmc.atom 3 ,
907 .Xr pmc.core 3 ,
908 .Xr pmc.corei7 3 ,
909 .Xr pmc.corei7uc 3 ,
910 .Xr pmc.iaf 3 ,
911 .Xr pmc.ivybridge 3 ,
912 .Xr pmc.ivybridgexeon 3 ,
913 .Xr pmc.sandybridgeuc 3 ,
914 .Xr pmc.sandybridgexeon 3 ,
915 .Xr pmc.soft 3 ,
916 .Xr pmc.tsc 3 ,
917 .Xr pmc.ucf 3 ,
918 .Xr pmc.westmere 3 ,
919 .Xr pmc.westmereuc 3 ,
920 .Xr pmc_cpuinfo 3 ,
921 .Xr pmclog 3 ,
929 .An -nosplit