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/linux/arch/riscv/kvm/
H A Daia.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/irqchip/riscv-imsic.h>
50 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts() local
51 unsigned long mask, val; in kvm_riscv_vcpu_aia_flush_interrupts() local
56 if (READ_ONCE(vcpu->arch.irqs_pending_mask[1])) { in kvm_riscv_vcpu_aia_flush_interrupts()
57 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[1], 0); in kvm_riscv_vcpu_aia_flush_interrupts()
58 val = READ_ONCE(vcpu->arch.irqs_pending[1]) & mask; in kvm_riscv_vcpu_aia_flush_interrupts()
60 csr->hviph &= ~mask; in kvm_riscv_vcpu_aia_flush_interrupts()
61 csr->hviph |= val; in kvm_riscv_vcpu_aia_flush_interrupts()
67 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_sync_interrupts() local
[all …]
H A Dvcpu.c1 // SPDX-License-Identifier: GPL-2.0
57 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_context_reset() local
58 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_vcpu_context_reset()
59 void *vector_datap = cntx->vector.datap; in kvm_riscv_vcpu_context_reset()
62 memset(csr, 0, sizeof(*csr)); in kvm_riscv_vcpu_context_reset()
63 memset(&vcpu->arch.smstateen_csr, 0, sizeof(vcpu->arch.smstateen_csr)); in kvm_riscv_vcpu_context_reset()
66 cntx->vector.datap = vector_datap; in kvm_riscv_vcpu_context_reset()
72 cntx->sstatus = SR_SPP | SR_SPIE; in kvm_riscv_vcpu_context_reset()
74 cntx->hstatus |= HSTATUS_VTW; in kvm_riscv_vcpu_context_reset()
75 cntx->hstatus |= HSTATUS_SPVP; in kvm_riscv_vcpu_context_reset()
[all …]
H A Dvcpu_insn.c1 // SPDX-License-Identifier: GPL-2.0
14 unsigned long mask; member
19 * 2) Returns 0 for exit to user-space
36 utrap.sepc = vcpu->arch.guest_context.sepc; in truly_illegal_insn()
52 utrap.sepc = vcpu->arch.guest_context.sepc; in truly_virtual_insn()
63 * kvm_riscv_vcpu_wfi -- Emulate wait for interrupt (WFI) behaviour
78 vcpu->stat.wfi_exit_stat++; in wfi_insn()
85 vcpu->stat.wrs_exit_stat++; in wrs_insn()
86 kvm_vcpu_on_spin(vcpu, vcpu->arch.guest_context.sstatus & SR_SPP); in wrs_insn()
106 if (!riscv_isa_extension_available(vcpu->arch.isa, ZKR)) in seed_csr_rmw()
[all …]
/linux/arch/loongarch/include/asm/
H A Dkvm_csr.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
14 #define gcsr_read(csr) \ argument
20 : [reg] "i" (csr) \
25 #define gcsr_write(v, csr) \ argument
31 : [reg] "i" (csr) \
36 #define gcsr_xchg(v, m, csr) \ argument
40 " gcsrxchg %[val], %[mask], %[reg]\n\t" \
42 : [mask] "r" (m), [reg] "i" (csr) \
182 #define kvm_save_hw_gcsr(csr, gid) (csr->csrs[gid] = gcsr_read(gid)) argument
[all …]
/linux/drivers/power/reset/
H A Dxgene-reboot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene SoC Reboot Driver
9 * This driver provides system reboot functionality for APM X-Gene SoC.
11 * implements GPIO shutdown, use the gpio-poweroff.c driver.
25 void __iomem *csr; member
26 u32 mask; member
31 struct xgene_reboot_context *ctx = data->cb_data; in xgene_restart_handler()
34 writel(ctx->mask, ctx->csr); in xgene_restart_handler()
38 dev_emerg(ctx->dev, "Unable to restart system\n"); in xgene_restart_handler()
46 struct device *dev = &pdev->dev; in xgene_reboot_probe()
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-interrupt-rsl.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-asxx-defs.h>
36 #include <asm/octeon/cvmx-gmxx-defs.h>
48 * @block: Interface to enable 0-1
52 int mask; in __cvmx_interrupt_asxx_enable() local
53 union cvmx_asxx_int_en csr; in __cvmx_interrupt_asxx_enable() local
60 mask = 0xf; /* Set enables for 4 ports */ in __cvmx_interrupt_asxx_enable()
62 mask = 0x7; /* Set enables for 3 ports */ in __cvmx_interrupt_asxx_enable()
[all …]
/linux/arch/alpha/kernel/
H A Dsys_titan.c1 // SPDX-License-Identifier: GPL-2.0
50 * Mask is set (1) if enabled
55 * Need SMP-safe access to interrupt CSRs
60 titan_update_irq_hw(unsigned long mask) in titan_update_irq_hw() argument
72 mask &= ~isa_enable; in titan_update_irq_hw()
73 mask0 = mask & titan_cpu_irq_affinity[0]; in titan_update_irq_hw()
74 mask1 = mask & titan_cpu_irq_affinity[1]; in titan_update_irq_hw()
75 mask2 = mask & titan_cpu_irq_affinity[2]; in titan_update_irq_hw()
76 mask3 = mask & titan_cpu_irq_affinity[3]; in titan_update_irq_hw()
83 dim0 = &cchip->dim0.csr; in titan_update_irq_hw()
[all …]
H A Dsys_dp264.c1 // SPDX-License-Identifier: GPL-2.0
39 /* Note mask bit is true for ENABLED irqs. */
47 tsunami_update_irq_hw(unsigned long mask) in tsunami_update_irq_hw() argument
57 mask &= ~isa_enable; in tsunami_update_irq_hw()
58 mask0 = mask & cpu_irq_affinity[0]; in tsunami_update_irq_hw()
59 mask1 = mask & cpu_irq_affinity[1]; in tsunami_update_irq_hw()
60 mask2 = mask & cpu_irq_affinity[2]; in tsunami_update_irq_hw()
61 mask3 = mask & cpu_irq_affinity[3]; in tsunami_update_irq_hw()
68 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
[all …]
/linux/drivers/usb/gadget/udc/
H A Dat91_udc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * at91_udc -- driver for at91-series USB peripheral controller
33 #include <linux/mfd/syscon/atmel-matrix.h>
39 * This controller is simple and PIO-only. It's used in many AT91-series
41 * at91sam926x (arm926ejs, with MMU), and several no-mmu versions.
76 EP_INFO("ep3-int",
91 __raw_readl((udc)->udp_baseaddr + (reg))
93 __raw_writel((val), (udc)->udp_baseaddr + (reg))
95 /*-------------------------------------------------------------------------*/
109 "control", "out-iso", "out-bulk", "out-int", in proc_ep_show()
[all …]
/linux/drivers/dma/
H A Dtegra186-gpc-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/dma-mapping.h>
21 #include <dt-bindings/memory/tegra186-mc.h>
22 #include "virt-dma.h"
24 /* CSR register */
118 (GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT)
158 * on-flight burst and update DMA status register.
166 /* Default channel mask reserving channel0 */
189 u32 csr; member
[all …]
/linux/drivers/clk/
H A Dclk-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
14 #include <linux/clk-provider.h>
32 static inline u32 xgene_clk_read(void __iomem *csr) in xgene_clk_read() argument
34 return readl_relaxed(csr); in xgene_clk_read()
37 static inline void xgene_clk_write(u32 data, void __iomem *csr) in xgene_clk_write() argument
39 writel_relaxed(data, csr); in xgene_clk_write()
64 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
82 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
84 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
[all …]
/linux/arch/alpha/include/asm/
H A Dcore_t2.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 * memory controller and PCI access for the SABLE-based systems.
25 #define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */
27 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
87 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
90 * +--------------+ 3 8000 0000
92 * +--------------+ 3 8100 0000
94 * +--------------+ 3 8200 0000
96 * +--------------+ 3 8300 0000
98 * +--------------+ 3 8400 0000
[all …]
/linux/include/linux/
H A Drio_regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 #define RIO_ASM_ID_MASK 0xffff0000 /* [I] Asm ID Mask */
23 #define RIO_ASM_VEN_ID_MASK 0x0000ffff /* [I] Asm Vend Mask */
26 #define RIO_ASM_REV_MASK 0xffff0000 /* [I] Asm Rev Mask */
27 #define RIO_EXT_FTR_PTR_MASK 0x0000ffff /* [I] EF_PTR Mask */
60 #define RIO_SRC_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
69 #define RIO_SRC_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
74 #define RIO_DST_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
83 #define RIO_DST_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
87 #define RIO_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
[all …]
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp6000_pcie.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
98 #define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize)
99 #define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize)
100 #define NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(bar, x) ((x) << ((bar)->bitsize - 2))
101 #define NFP_PCIE_P2C_GENERAL_TOKEN_OFFSET(bar, x) ((x) << ((bar)->bitsize - 4))
102 #define NFP_PCIE_P2C_GENERAL_SIZE(bar) (1 << ((bar)->bitsize - 4))
116 * struct nfp_bar - describes BAR configuration and usage
118 * @barcfg: cached contents of BAR config CSR
120 * @mask: mask for the BAR aperture (read only)
[all …]
/linux/sound/sparc/
H A Dcs4231.c1 // SPDX-License-Identifier: GPL-2.0-only
41 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
121 * now.... -DaveM
125 #include <sound/cs4231-regs.h>
128 #define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
132 #define APCCSR 0x10UL /* APC DMA CSR */
142 /* Defines for SBUS DMA-routine
306 snd_cs4231_outm(struct snd_cs4231 * chip,unsigned char reg,unsigned char mask,unsigned char value) snd_cs4231_outm() argument
1328 int mask = (kcontrol->private_value >> 16) & 0xff; snd_cs4231_info_single() local
1346 int mask = (kcontrol->private_value >> 16) & 0xff; snd_cs4231_get_single() local
1369 int mask = (kcontrol->private_value >> 16) & 0xff; snd_cs4231_put_single() local
1393 int mask = (kcontrol->private_value >> 24) & 0xff; snd_cs4231_info_double() local
1413 int mask = (kcontrol->private_value >> 24) & 0xff; snd_cs4231_get_double() local
1444 int mask = (kcontrol->private_value >> 24) & 0xff; snd_cs4231_put_double() local
1472 CS4231_SINGLE(xname,xindex,reg,shift,mask,invert) global() argument
1479 CS4231_DOUBLE(xname,xindex,left_reg,right_reg,shift_left,shift_right,mask,invert) global() argument
1615 u32 csr; snd_cs4231_sbus_interrupt() local
1665 u32 test, csr; sbus_dma_request() local
1696 u32 csr, test; sbus_dma_prepare() local
1715 u32 csr, shift; sbus_dma_enable() local
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/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
28 +-+-+-+-+-+-+-+-+
[all …]
/linux/arch/mips/dec/
H A Dkn02-irq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * Bits 7:0 of the Control Register are write-only -- the
22 * There is no default value -- it has to be initialized.
30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
33 cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16)); in unmask_kn02_irq()
34 *csr = cached_kn02_csr; in unmask_kn02_irq()
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
42 cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16)); in mask_kn02_irq()
43 *csr = cached_kn02_csr; in mask_kn02_irq()
53 .name = "KN02-CSR",
[all …]
/linux/drivers/usb/musb/
H A Dux500_dma.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Copyright (C) 2011 ST-Ericsson SA
18 #include <linux/dma-mapping.h>
22 #include <linux/platform_data/usb-musb-ux500.h>
54 struct ux500_dma_channel *ux500_channel = channel->private_data; in ux500_dma_callback()
55 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; in ux500_dma_callback()
56 struct musb *musb = hw_ep->musb; in ux500_dma_callback()
59 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", in ux500_dma_callback()
60 hw_ep->epnum); in ux500_dma_callback()
62 spin_lock_irqsave(&musb->lock, flags); in ux500_dma_callback()
[all …]
/linux/arch/loongarch/kvm/
H A Dvcpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
44 context = this_cpu_ptr(vcpu->kvm->arch.vmcs); in kvm_save_host_pmu()
45 context->perf_cntr[0] = read_csr_perfcntr0(); in kvm_save_host_pmu()
46 context->perf_cntr[1] = read_csr_perfcntr1(); in kvm_save_host_pmu()
47 context->perf_cntr[2] = read_csr_perfcntr2(); in kvm_save_host_pmu()
48 context->perf_cntr[3] = read_csr_perfcntr3(); in kvm_save_host_pmu()
49 context->perf_ctrl[0] = write_csr_perfctrl0(0); in kvm_save_host_pmu()
50 context->perf_ctrl[1] = write_csr_perfctrl1(0); in kvm_save_host_pmu()
51 context->perf_ctrl[2] = write_csr_perfctrl2(0); in kvm_save_host_pmu()
[all …]
/linux/drivers/tty/serial/
H A Drsci.c1 // SPDX-License-Identifier: GPL-2.0
28 #define CSR 0x48 macro
58 #define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */
76 /* CSR (Common Status Register) */
90 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
91 #define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear)
126 return readl(p->membase + offset); in rsci_serial_in()
131 writel(value, p->membase + offset); in rsci_serial_out()
140 static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask) in rsci_clear_SCxSR() argument
142 rsci_serial_out(port, CFCLR, mask); in rsci_clear_SCxSR()
[all …]
/linux/arch/mips/kernel/
H A Dsignal.c7 * Copyright (C) 1994 - 2000 Ralf Baechle
37 #include <asm/cpu-features.h>
43 #include "signal-common.h"
73 struct mips_abi *abi = current->thread.abi; in copy_fp_to_sigcontext()
74 uint64_t __user *fpregs = sc + abi->off_sc_fpregs; in copy_fp_to_sigcontext()
75 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; in copy_fp_to_sigcontext() local
82 __put_user(get_fpr64(&current->thread.fpu.fpr[i], 0), in copy_fp_to_sigcontext()
85 err |= __put_user(current->thread.fpu.fcr31, csr); in copy_fp_to_sigcontext()
92 struct mips_abi *abi = current->thread.abi; in copy_fp_from_sigcontext()
93 uint64_t __user *fpregs = sc + abi->off_sc_fpregs; in copy_fp_from_sigcontext()
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma3.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
24 #include "../virt-dma.h"
56 /* MISR DMA non-secure/secure masked interrupt status register */
140 CTR1_PAM_0S_LT, /* if DDW > SDW, padded with 0s else left-truncated */
141 CTR1_PAM_SE_RT, /* if DDW > SDW, sign extended else right-truncated */
163 /* CxLLR DMA channel x linked-list address register */
180 #define get_chan_hwcfg(x, mask, reg) (((reg) & (mask)) >> (4 * (x))) argument
192 AXI64, /* 1x AXI: 64-bit port 0 */
193 AHB32, /* 1x AHB: 32-bit port 0 */
[all …]
/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 * Layout of a DMAC Linked-List Descriptor
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
85 * GCSR - Global Control and Status Registers
86 * CR/CSR - Subset of Configuration ROM /
379 * Inbound Translation CR/CSR
489 * offset 0x00 0x600 - DEVI/VENI
[all …]
/linux/arch/mips/include/asm/sibyte/
H A Dsb1250_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 * 'long long' (64-bit integer) support.
35 * SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
78 * Mask values currently include room for additional revisions of each
97 /* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
120 /* Bit mask for revisions of chip exclusively before the named revision. */
122 ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
124 /* Bit mask for revisions of chip exclusively after the named revision. */
127 | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
158 * M_xxx MASK constant (identifies bits in a register).
[all …]
/linux/drivers/usb/mtu3/
H A Dmtu3_core.c1 // SPDX-License-Identifier: GPL-2.0
3 * mtu3_core.c - hardware access layer and gadget init/exit of
4 * MediaTek usb3 Dual-Role Controller Driver
11 #include <linux/dma-mapping.h>
25 struct mtu3_fifo_info *fifo = mep->fifo; in ep_fifo_alloc()
29 /* ensure that @mep->fifo_seg_size is power of two */ in ep_fifo_alloc()
31 if (num_bits > fifo->limit) in ep_fifo_alloc()
32 return -EINVAL; in ep_fifo_alloc()
34 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT; in ep_fifo_alloc()
35 num_bits = num_bits * (mep->slot + 1); in ep_fifo_alloc()
[all …]

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