Lines Matching +full:csr +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 * 'long long' (64-bit integer) support.
35 * SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
78 * Mask values currently include room for additional revisions of each
97 /* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
120 /* Bit mask for revisions of chip exclusively before the named revision. */
122 ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
124 /* Bit mask for revisions of chip exclusively after the named revision. */
127 | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
158 * M_xxx MASK constant (identifies bits in a register).
159 * For multi-bit fields, all bits in the field will
162 * K_xxx "Code" constant (value for data in a multi-bit
182 * G_xxx(X) GET value. This macro obtains a multi-bit field
196 * Cast to 64-bit number. Presumably the syntax is different in
212 * Make a mask for 1 bit at position 'n'
219 * Make a mask for 'v' bits at position 'n'
222 #define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
223 #define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
236 * Macros to read/write on-chip registers
242 #define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val) argument
243 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr))) argument