Lines Matching +full:csr +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * Bits 7:0 of the Control Register are write-only -- the
22 * There is no default value -- it has to be initialized.
30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
33 cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16)); in unmask_kn02_irq()
34 *csr = cached_kn02_csr; in unmask_kn02_irq()
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
42 cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16)); in mask_kn02_irq()
43 *csr = cached_kn02_csr; in mask_kn02_irq()
53 .name = "KN02-CSR",
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local
66 /* Mask interrupts. */ in init_kn02_irqs()
68 *csr = cached_kn02_csr; in init_kn02_irqs()