1 // SPDX-License-Identifier: GPL-2.0
50  * Mask is set (1) if enabled
55  * Need SMP-safe access to interrupt CSRs
60 titan_update_irq_hw(unsigned long mask)  in titan_update_irq_hw()  argument
72 	mask &= ~isa_enable;  in titan_update_irq_hw()
73 	mask0 = mask & titan_cpu_irq_affinity[0];  in titan_update_irq_hw()
74 	mask1 = mask & titan_cpu_irq_affinity[1];  in titan_update_irq_hw()
75 	mask2 = mask & titan_cpu_irq_affinity[2];  in titan_update_irq_hw()
76 	mask3 = mask & titan_cpu_irq_affinity[3];  in titan_update_irq_hw()
83 	dim0 = &cchip->dim0.csr;  in titan_update_irq_hw()
84 	dim1 = &cchip->dim1.csr;  in titan_update_irq_hw()
85 	dim2 = &cchip->dim2.csr;  in titan_update_irq_hw()
86 	dim3 = &cchip->dim3.csr;  in titan_update_irq_hw()
103 	dimB = &cchip->dim0.csr;  in titan_update_irq_hw()
104 	if (bcpu == 1) dimB = &cchip->dim1.csr;  in titan_update_irq_hw()
105 	else if (bcpu == 2) dimB = &cchip->dim2.csr;  in titan_update_irq_hw()
106 	else if (bcpu == 3) dimB = &cchip->dim3.csr;  in titan_update_irq_hw()
108 	*dimB = mask | isa_enable;  in titan_update_irq_hw()
117 	unsigned int irq = d->irq;  in titan_enable_irq()
119 	titan_cached_irq_mask |= 1UL << (irq - 16);  in titan_enable_irq()
127 	unsigned int irq = d->irq;  in titan_disable_irq()
129 	titan_cached_irq_mask &= ~(1UL << (irq - 16));  in titan_disable_irq()
152 	unsigned int irq = d->irq;  in titan_set_irq_affinity()
154 	titan_cpu_set_irq_affinity(irq - 16, *affinity);  in titan_set_irq_affinity()
172 	irq = (vector - 0x800) >> 4;  in titan_srm_device_interrupt()
200        * event counting -- just return.  in titan_intr_nop()
235 titan_dispatch_irqs(u64 mask)  in titan_dispatch_irqs()  argument
240 	 * Mask down to those interrupts which are enable on this processor  in titan_dispatch_irqs()
242 	mask &= titan_cpu_irq_affinity[smp_processor_id()];  in titan_dispatch_irqs()
247 	while (mask) {  in titan_dispatch_irqs()
248 		/* convert to SRM vector... priority is <63> -> <0> */  in titan_dispatch_irqs()
249 		vector = 63 - __kernel_ctlz(mask);  in titan_dispatch_irqs()
250 		mask &= ~(1UL << vector);	/* clear it out 	 */  in titan_dispatch_irqs()
320  	/* Offset by 16 to make room for ISA interrupts 0 - 15.  */  in titan_map_irq()