| /linux/drivers/media/platform/qcom/venus/ |
| H A D | hfi_parser.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include "core.h"
17 static void init_codecs(struct venus_core *core) in init_codecs() argument
19 struct hfi_plat_caps *caps = core->caps, *cap; in init_codecs()
22 if (hweight_long(core->dec_codecs) + hweight_long(core->enc_codecs) > MAX_CODEC_NUM) in init_codecs()
25 for_each_set_bit(bit, &core->dec_codecs, MAX_CODEC_NUM) { in init_codecs()
26 cap = &caps[core->codecs_count++]; in init_codecs()
27 cap->codec = BIT(bit); in init_codecs()
28 cap->domain = VIDC_SESSION_TYPE_DEC; in init_codecs()
29 cap->valid = false; in init_codecs()
[all …]
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| /linux/arch/arm/mach-omap2/ |
| H A D | powerdomains44xx_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009-2011 Texas Instruments, Inc.
6 * Copyright (C) 2009-2011 Nokia Corporation
9 * Benoit Cousson (b-cousson@ti.com)
14 * with the public linux-omap@vger.kernel.org mailing list and the
16 * up-to-date with the file contents.
24 #include "prcm-common.h"
26 #include "prm-regbits-44xx.h"
30 /* core_44xx_pwrdm: CORE power domain */
33 .voltdm = { .name = "core" },
[all …]
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| H A D | powerdomains54xx_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Benoit Cousson (b-cousson@ti.com)
13 * with the public linux-omap@vger.kernel.org mailing list and the
15 * up-to-date with the file contents.
23 #include "prcm-common.h"
28 /* core_54xx_pwrdm: CORE power domain */
31 .voltdm = { .name = "core" },
54 /* abe_54xx_pwrdm: Audio back end power domain */
57 .voltdm = { .name = "core" },
74 /* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
[all …]
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| /linux/Documentation/networking/ |
| H A D | regulatory.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------
19 to the kernel one regulatory domain to be used as the central
20 core regulatory domain all wireless devices should adhere to.
23 -------------------------------------------
25 When the regulatory domain is first set up, the kernel will request a
31 ---------------------------------------------------------------
33 Userspace gets a regulatory domain in the kernel by having
38 is CRDA - central regulatory domain agent. Its documented here:
43 it needs a new regulatory domain. A udev rule can be put in place
[all …]
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | renesas,rzg2l-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
20 1. Module Standby, providing a Clock Domain to control the clock supply
27 - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
[all …]
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| H A D | renesas,cpg-mssr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
20 1. Module Standby, providing a Clock Domain to control the clock supply
27 - renesas,r7s9210-cpg-mssr # RZ/A2
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| /linux/arch/arm64/boot/dts/apple/ |
| H A D | t8103-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
23 #reset-cells = <0>;
[all …]
|
| H A D | t8112-pmgr.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
23 #reset-cells = <0>;
[all …]
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| /linux/Documentation/devicetree/bindings/soc/tegra/ |
| H A D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
[all …]
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| /linux/arch/powerpc/perf/ |
| H A D | hv-24x7-domains.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * DOMAIN(name, num, index_kind, is_physical)
9 * @num: The number corresponding to the domain as given in
10 * documentation. We assume the catalog domain and the hcall
11 * domain have the same numbering (so far they do), but this
15 * within the given domain. Must fit the parsing rules of the
18 * @is_physical: True if the domain is physical, false otherwise (if virtual).
21 * physical core and virtual processor in 24x7 Counters specifications.
24 DOMAIN(PHYS_CHIP, 0x01, chip, true)
25 DOMAIN(PHYS_CORE, 0x02, core, true)
[all …]
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | qcom,sc7180-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sc7180-adsp-pas
20 - qcom,sc7180-mpss-pas
21 - qcom,sc7280-adsp-pas
22 - qcom,sc7280-cdsp-pas
23 - qcom,sc7280-mpss-pas
[all …]
|
| H A D | qcom,sm6350-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6350-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sm6350-adsp-pas
20 - qcom,sm6350-cdsp-pas
21 - qcom,sm6350-mpss-pas
28 - description: XO clock
30 clock-names:
[all …]
|
| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
|
| H A D | qcom,sm8350-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm8350-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sm8350-adsp-pas
20 - qcom,sm8350-cdsp-pas
21 - qcom,sm8350-slpi-pas
22 - qcom,sm8350-mpss-pas
23 - qcom,sm8450-adsp-pas
[all …]
|
| H A D | qcom,msm8916-mss-pil.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
14 firmware on the Qualcomm MSM8916 Modem Hexagon Core (and similar).
19 - enum:
20 - qcom,msm8909-mss-pil
21 - qcom,msm8916-mss-pil
22 - qcom,msm8953-mss-pil
[all …]
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| H A D | qcom,sm8150-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm8150-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sm8150-adsp-pas
20 - qcom,sm8150-cdsp-pas
21 - qcom,sm8150-mpss-pas
22 - qcom,sm8150-slpi-pas
23 - qcom,sm8250-adsp-pas
[all …]
|
| H A D | qcom,sm6375-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6375-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sm6375-adsp-pas
20 - qcom,sm6375-cdsp-pas
21 - qcom,sm6375-mpss-pas
28 - description: XO clock
30 clock-names:
[all …]
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| H A D | qcom,adsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 firmware on the Qualcomm ADSP Hexagon core.
19 - qcom,msm8226-adsp-pil
20 - qcom,msm8953-adsp-pil
21 - qcom,msm8974-adsp-pil
22 - qcom,msm8996-adsp-pil
23 - qcom,msm8996-slpi-pil
[all …]
|
| H A D | qcom,sc8280xp-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sc8280xp-adsp-pas
20 - qcom,sc8280xp-nsp0-pas
21 - qcom,sc8280xp-nsp1-pas
28 - description: XO clock
30 clock-names:
[all …]
|
| H A D | qcom,sa8775p-pas.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sa8775p-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
19 - qcom,sa8775p-adsp-pas
20 - qcom,sa8775p-cdsp0-pas
21 - qcom,sa8775p-cdsp1-pas
22 - qcom,sa8775p-gpdsp0-pas
23 - qcom,sa8775p-gpdsp1-pas
[all …]
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| /linux/include/net/ |
| H A D | regulatory.h | 7 * Copyright 2008-2009 Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
28 * enum environment_cap - Environment parsed from country IE
41 * struct regulatory_request - used to keep track of regulatory requests
46 * can be used by the wireless core to deal with conflicts
52 * regulatory domain. We have a few special codes:
53 * 00 - World regulatory domain
54 * 99 - built by driver but a specific alpha2 cannot be determined
55 * 98 - result of an intersection between two regulatory domains
56 * 97 - regulatory domain has not yet been configured
57 * @dfs_region: If CRDA responded with a regulatory domain that requires
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/imx/ |
| H A D | fsl,imx8mm-disp-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
15 peripherals located in the DISP domain of the SoC.
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
[all …]
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| /linux/arch/arm64/boot/dts/qcom/ |
| H A D | sdm670.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
[all …]
|
| /linux/Documentation/devicetree/bindings/regulator/ |
| H A D | nvidia,tegra-regulators-coupling.txt | 4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
25 as the "Core domain" voltage regulator.
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
[all …]
|
| /linux/kernel/irq/ |
| H A D | ipi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
16 * @domain: IPI domain
23 int irq_reserve_ipi(struct irq_domain *domain, in irq_reserve_ipi() argument
30 if (!domain ||!irq_domain_is_ipi(domain)) { in irq_reserve_ipi()
31 pr_warn("Reservation on a non IPI domain\n"); in irq_reserve_ipi()
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
46 if (irq_domain_is_ipi_single(domain)) { in irq_reserve_ipi()
[all …]
|