Lines Matching +full:core +full:- +full:domain
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
20 1. Module Standby, providing a Clock Domain to control the clock supply
27 - renesas,r7s9210-cpg-mssr # RZ/A2
28 - renesas,r8a7742-cpg-mssr # RZ/G1H
29 - renesas,r8a7743-cpg-mssr # RZ/G1M
30 - renesas,r8a7744-cpg-mssr # RZ/G1N
31 - renesas,r8a7745-cpg-mssr # RZ/G1E
32 - renesas,r8a77470-cpg-mssr # RZ/G1C
33 - renesas,r8a774a1-cpg-mssr # RZ/G2M
34 - renesas,r8a774a3-cpg-mssr # RZ/G2M v3.0
35 - renesas,r8a774b1-cpg-mssr # RZ/G2N
36 - renesas,r8a774c0-cpg-mssr # RZ/G2E
37 - renesas,r8a774e1-cpg-mssr # RZ/G2H
38 - renesas,r8a7790-cpg-mssr # R-Car H2
39 - renesas,r8a7791-cpg-mssr # R-Car M2-W
40 - renesas,r8a7792-cpg-mssr # R-Car V2H
41 - renesas,r8a7793-cpg-mssr # R-Car M2-N
42 - renesas,r8a7794-cpg-mssr # R-Car E2
43 - renesas,r8a7795-cpg-mssr # R-Car H3
44 - renesas,r8a7796-cpg-mssr # R-Car M3-W
45 - renesas,r8a77961-cpg-mssr # R-Car M3-W+
46 - renesas,r8a77965-cpg-mssr # R-Car M3-N
47 - renesas,r8a77970-cpg-mssr # R-Car V3M
48 - renesas,r8a77980-cpg-mssr # R-Car V3H
49 - renesas,r8a77990-cpg-mssr # R-Car E3
50 - renesas,r8a77995-cpg-mssr # R-Car D3
51 - renesas,r8a779a0-cpg-mssr # R-Car V3U
52 - renesas,r8a779f0-cpg-mssr # R-Car S4-8
53 - renesas,r8a779g0-cpg-mssr # R-Car V4H
54 - renesas,r8a779h0-cpg-mssr # R-Car V4M
63 clock-names:
68 - extal # All
69 - extalr # Most R-Car Gen3 and RZ/G2
70 - usb_extal # Most R-Car Gen2 and RZ/G1
72 '#clock-cells':
74 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
75 and a core clock reference, as defined in
76 <dt-bindings/clock/*-cpg-mssr.h>
77 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
81 '#power-domain-cells':
83 SoC devices that are part of the CPG/MSSR Clock Domain and can be
84 power-managed through Module Standby should refer to the CPG device node
85 in their "power-domains" property, as documented by the generic PM Domain
86 bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
89 '#reset-cells':
101 - renesas,r7s9210-cpg-mssr
104 - '#reset-cells'
107 - compatible
108 - reg
109 - clocks
110 - clock-names
111 - '#clock-cells'
112 - '#power-domain-cells'
117 - |
118 cpg: clock-controller@e6150000 {
119 compatible = "renesas,r8a7795-cpg-mssr";
122 clock-names = "extal", "extalr";
123 #clock-cells = <2>;
124 #power-domain-cells = <0>;
125 #reset-cells = <1>;