| /linux/drivers/ufs/host/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0+
3 # Kernel configuration file for the UFS host controller drivers.
5 # Copyright (C) 2011-2013 Samsung India Software Operations
12 tristate "PCI bus based UFS Controller support"
15 This selects the PCI UFS Host Controller Interface. Select this if
16 you have UFS Host Controller with PCI Interface.
18 If you have a controller with this interface, say Y or M here.
31 tristate "Platform bus based UFS Controller support"
34 This selects the UFS host controller support. Select this if
35 you have an UFS controller on Platform bus.
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| /linux/drivers/pci/controller/dwc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
14 Say Y here to enable debugfs entries for the PCIe controller. These
15 entries provide various debug features related to the controller and
30 bool "Amazon Annapurna Labs PCIe controller"
37 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
39 required only for DT-based platforms. ACPI platforms with the
40 Annapurna Labs PCIe controller don't need to enable this.
43 bool "AMD MDB Versal2 PCIe controller"
48 Say Y here if you want to enable PCIe controller support on AMD
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
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| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
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| H A D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC PCIe RP/EP controller
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
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| /linux/Documentation/devicetree/bindings/input/ |
| H A D | brcm,bcm-keypad.txt | 1 * Broadcom Keypad Controller device tree bindings
3 Broadcom Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be "brcm,bcm-keypad"
17 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: The interrupt number to the cpu.
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| /linux/include/linux/ |
| H A D | peci.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2018-2021 Intel Corporation */
21 * struct peci_controller_ops - PECI controller specific methods
24 * PECI controllers may have different hardware interfaces - the drivers
29 int (*xfer)(struct peci_controller *controller, u8 addr, struct peci_request *req);
33 * struct peci_controller - PECI controller
34 * @dev: device object to register PECI controller to the device model
35 * @ops: pointer to device specific controller operations
37 * @id: PECI controller ID
39 * PECI controllers usually connect to their drivers using non-PECI bus,
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | k3-dw-mshc.txt | 1 * Hisilicon specific extensions to the Synopsys Designware Mobile
2 Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
10 extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
17 with hi3670 specific extensions.
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| H A D | bluefield-dw-mshc.txt | 1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
2 Mobile Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
10 specific extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
16 specific extensions.
22 compatible = "mellanox,bluefield-dw-mshc";
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| /linux/drivers/nvme/host/ |
| H A D | fabrics.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2015-2016 HGST, a Western Digital Company.
18 /* default is -1: the fail fast mechanism is disabled */
19 #define NVMF_DEF_FAIL_FAST_TMO -1
37 * enum nvmf_parsing_opts - used to define the sysfs parsing options used.
73 * struct nvmf_ctrl_options - Used to hold the options specified
76 * on adding a NVMe controller.
78 * the controller, (-1) means reconnect forever, zero means remove
81 * better description) that will be used by an NVMe controller
85 * @traddr: The transport-specific TRADDR field for a port on the
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-led-flash | 55 Flash faults are re-read after strobing the flash. Possible
58 * led-over-voltage
59 flash controller voltage to the flash LED
60 has exceeded the limit specific to the flash controller
61 * flash-timeout-exceeded
65 * controller-over-temperature
66 the flash controller has
68 * controller-short-circuit
70 of the flash controller has been triggered
71 * led-power-supply-over-current
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| /linux/drivers/platform/mips/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MIPS Platform Specific Drivers
7 bool "MIPS Platform Specific Device Drivers"
12 MIPS platforms, including vendor-specific netbook/laptop/desktop
21 bool "Loongson-3 CPU HWMon Driver"
26 Loongson-3A/3B CPU Hwmon (temperature sensor) driver.
29 bool "Loongson RS780E ACPI Controller"
32 Loongson RS780E PCH ACPI Controller driver.
35 bool "Loongson-2K1000 Reset Controller"
38 Loongson-2K1000 Reset Controller driver.
|
| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | pamu.txt | 5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
15 I/O space utilized by the controller. The size should
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
31 - reg : <prop-encoded-array>
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| /linux/Documentation/spi/ |
| H A D | spi-summary.rst | 5 02-Feb-2012
8 ------------
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
38 - Some devices may use eight bit words. Others may use different word
39 lengths, such as streams of 12-bit or 20-bit digital samples.
41 - Words are usually sent with their most significant bit (MSB) first,
44 - Sometimes SPI is used to daisy-chain devices, like shift registers.
48 a given SPI host controller will normally be set up manually, with
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| /linux/Documentation/scsi/ |
| H A D | hpsa.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 HPSA - Hewlett Packard Smart Array driver
12 "split-brained" design of the cciss driver is a source of excess
19 - Smart Array P212
20 - Smart Array P410
21 - Smart Array P410i
22 - Smart Array P411
23 - Smart Array P812
24 - Smart Array P712m
25 - Smart Array P711m
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | ext-ctrls-flash.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _flash-controls:
10 controller devices. Flash controller devices are typically used in
17 .. _flash-controls-use-cases:
24 ------------------------------------------
35 ----------------------------------------
37 The synchronised LED flash is pre-programmed by the host (power and
46 ------------------
52 .. _flash-control-id:
55 -----------------
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| /linux/Documentation/devicetree/bindings/display/hisilicon/ |
| H A D | dw-dsi.txt | 1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
17 A example of HiKey board hi6220 SoC and board specific DT entry:
20 SoC specific:
22 compatible = "hisilicon,hi6220-dsi";
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| /linux/drivers/clk/ |
| H A D | clk-aspeed.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
17 * struct aspeed_gate_data - Aspeed gated clocks
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
40 * @flags: hardware-specific flags
59 * struct aspeed_reset - Aspeed reset controller
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | mediatek,mtk-xhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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| H A D | omap-usb.txt | 1 OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
12 interface between the controller and the phy. It should be "0" or "1"
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
12 be controller specific like delay in clock or data lines, etc. These
14 per-peripheral and there can be multiple peripherals attached to a
15 controller. All those properties are listed here. The controller specific
20 - Mark Brown <broonie@kernel.org>
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| /linux/include/ufs/ |
| H A D | ufshcd.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
16 #include <linux/blk-crypto-profil
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| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
17 search using a specific compatible value), interrogate the node (or
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | fsl,imx-pinctrl.txt | 1 * Freescale IOMUX Controller (IOMUXC) for i.MX
3 The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, open drain, drive strength, etc.
20 Required properties for iomux controller:
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
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| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
17 registers and for its data input/output buffer. On some SoCs, this controller
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