| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller endpoint
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
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| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
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| /linux/arch/x86/include/asm/ |
| H A D | x86_init.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct x86_init_mpparse - platform specific mpparse ops
15 * @setup_ioapic_ids: platform specific ioapic id override
28 * struct x86_init_resources - platform specific resource related ops
32 * @memory_setup: platform specific memory setup
33 * @dmi_setup: platform specific DMI setup
43 * struct x86_init_irqs - platform specific interrupt setup
60 * struct x86_init_oem - oem platform specific customizing functions
61 * @arch_setup: platform specific architecture setup
62 * @banner: print a platform specific banner
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| /linux/Documentation/driver-api/usb/ |
| H A D | writing_musb_glue_layer.rst | 12 use Universal Host Controller Interface (UHCI) or Open Host Controller
15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
37 albeit focused on some specific devices provided by these companies.
42 Linux USB stack is a layered architecture in which the MUSB controller
43 hardware sits at the lowest. The MUSB controller driver abstract the
44 MUSB controller hardware to the Linux USB stack::
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| /linux/Documentation/devicetree/bindings/input/ |
| H A D | brcm,bcm-keypad.txt | 1 * Broadcom Keypad Controller device tree bindings
3 Broadcom Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be "brcm,bcm-keypad"
17 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: The interrupt number to the cpu.
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| H A D | omap-keypad.txt | 1 * TI's Keypad Controller device tree bindings
3 TI's Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be one of the following
16 - "ti,omap4-keypad": For controllers compatible with omap4 keypad
17 controller.
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| /linux/include/linux/ |
| H A D | peci.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2018-2021 Intel Corporation */
21 * struct peci_controller_ops - PECI controller specific methods
24 * PECI controllers may have different hardware interfaces - the drivers
29 int (*xfer)(struct peci_controller *controller, u8 addr, struct peci_request *req);
33 * struct peci_controller - PECI controller
34 * @dev: device object to register PECI controller to the device model
35 * @ops: pointer to device specific controller operations
37 * @id: PECI controller ID
39 * PECI controllers usually connect to their drivers using non-PECI bus,
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-led-flash | 55 Flash faults are re-read after strobing the flash. Possible
58 * led-over-voltage
59 flash controller voltage to the flash LED
60 has exceeded the limit specific to the flash controller
61 * flash-timeout-exceeded
65 * controller-over-temperature
66 the flash controller has
68 * controller-short-circuit
70 of the flash controller has been triggered
71 * led-power-supply-over-current
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | mediatek,mtk-xhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
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| /linux/Documentation/spi/ |
| H A D | spi-summary.rst | 5 02-Feb-2012
8 ------------
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
38 - Some devices may use eight bit words. Others may use different word
39 lengths, such as streams of 12-bit or 20-bit digital samples.
41 - Words are usually sent with their most significant bit (MSB) first,
44 - Sometimes SPI is used to daisy-chain devices, like shift registers.
48 a given SPI host controller will normally be set up manually, with
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| /linux/drivers/platform/mips/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MIPS Platform Specific Drivers
7 bool "MIPS Platform Specific Device Drivers"
12 MIPS platforms, including vendor-specific netbook/laptop/desktop
21 bool "Loongson-3 CPU HWMon Driver"
26 Loongson-3A/3B CPU Hwmon (temperature sensor) driver.
29 bool "Loongson RS780E ACPI Controller"
32 Loongson RS780E PCH ACPI Controller driver.
35 bool "Loongson-2K1000 Reset Controller"
38 Loongson-2K1000 Reset Controller driver.
|
| /linux/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | pamu.txt | 5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
15 I/O space utilized by the controller. The size should
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
31 - reg : <prop-encoded-array>
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| H A D | dcsr.txt | 21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
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| /linux/Documentation/scsi/ |
| H A D | hpsa.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 HPSA - Hewlett Packard Smart Array driver
12 "split-brained" design of the cciss driver is a source of excess
19 - Smart Array P212
20 - Smart Array P410
21 - Smart Array P410i
22 - Smart Array P411
23 - Smart Array P812
24 - Smart Array P712m
25 - Smart Array P711m
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | bluefield-dw-mshc.txt | 1 * Mellanox Bluefield SoC specific extensions to the Synopsys Designware
2 Mobile Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
10 specific extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
16 specific extensions.
22 compatible = "mellanox,bluefield-dw-mshc";
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| /linux/Documentation/devicetree/bindings/display/hisilicon/ |
| H A D | dw-dsi.txt | 1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
17 A example of HiKey board hi6220 SoC and board specific DT entry:
20 SoC specific:
22 compatible = "hisilicon,hi6220-dsi";
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| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
17 search using a specific compatible value), interrogate the node (or
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | fsl,imx-pinctrl.txt | 1 * Freescale IOMUX Controller (IOMUXC) for i.MX
3 The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
10 Please refer to pinctrl-bindings.txt in this directory for details of the
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, open drain, drive strength, etc.
20 Required properties for iomux controller:
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
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| H A D | mediatek,mt8365-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT8365 Pin Controller
10 - Zhiyong Tao <zhiyong.tao@mediatek.com>
11 - Bernhard Rosenkränzer <bero@baylibre.com>
14 The MediaTek's MT8365 Pin controller is used to control SoC pins.
18 const: mediatek,mt8365-pinctrl
23 mediatek,pctl-regmap:
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| /linux/drivers/pinctrl/mediatek/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
141 Say yes here to support pin controller and gpio driver
165 Say yes here to support pin controller and gpio driver
168 map specific eint which doesn't have real gpio pin.
191 Say yes here to support pin controller and gpio driver
201 Say yes here to support pin controller and gpio driver
267 Say yes here to support pin controller and gpio driver
270 map specific eint which doesn't have real gpio pin.
279 Say yes here to support pin controller and gpio driver
282 map specific eint which doesn't have real gpio pin.
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| /linux/include/linux/mtd/ |
| H A D | platnand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
18 * struct platform_nand_chip - chip level device structure
26 * @part_probe_types: NULL-terminated array of probe types
40 * struct platform_nand_ctrl - controller level device structure
41 * @probe: platform specific function to probe/setup hardware
42 * @remove: platform specific function to remove/teardown hardware
43 * @dev_ready: platform specific function to read ready/busy pin
44 * @select_chip: platform specific chip select function
45 * @cmd_ctrl: platform specific function for controlling
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| /linux/drivers/mtd/nand/raw/ |
| H A D | internals.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018 - Bootlin
8 * NAND controller drivers should not include this file.
38 * struct nand_manufacturer_ops - NAND Manufacturer operations
40 * @init: initialize all vendor specific fields (like the ->read_retry()
42 * @cleanup: the ->init() function may have allocated resources, ->cleanup()
43 * is here to let vendor specific code release those resources.
44 * @fixup_onfi_param_page: apply vendor specific fixups to the ONFI parameter
56 * struct nand_manufacturer_desc - NAND Flash Manufacturer descriptor
117 if (!chip->controller || !chip->controller->ops || in nand_has_exec_op()
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| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | syscon-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/syscon-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Controller Registers R/W Common Properties
10 System controller node represents a register region containing a set
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
15 search using a specific compatible value), interrogate the node (or
20 - Lee Jones <lee@kernel.org>
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | ti,keystone-dsp-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 DSP GPIO controller
10 - Grygorii Strashko <grygorii.strashko@ti.com>
14 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
18 - 8 for C66x CorePacx CPUs 0-7
20 Keystone 2 DSP GPIO controller has specific features:
21 - each GPIO can be configured only as output pin;
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| /linux/include/linux/spi/ |
| H A D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later
41 * INTERFACES between SPI controller-side drivers and SPI target protocol handlers,
47 * struct spi_statistics - statistics for spi transfers
48 * @syncp: seqcount to protect members in this struct for per-cpu update
49 * on 32-bit systems
51 * @messages: number of spi-messages handled
100 u64_stats_update_begin(&__lstats->syncp); \
101 u64_stats_add(&__lstats->field, count); \
102 u64_stats_update_end(&__lstats->syncp); \
111 u64_stats_update_begin(&__lstats->syncp); \
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