| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | via,vt8500-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/via,vt8500-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: VIA and WonderMedia SoCs Interrupt Controller
10 This is the interrupt controller used in single-core ARM SoCs made by
16 - Alexey Charkov <alchark@gmail.com>
19 - $ref: /schemas/interrupt-controller.yaml#
23 const: via,vt8500-intc
30 - description:
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| H A D | img,meta-intc.txt | 1 * Meta External Trigger Controller Binding
4 representation of a Meta external trigger controller.
8 - compatible: Specifies the compatibility list for the interrupt controller.
9 The type shall be <string> and the value shall include "img,meta-intc".
11 - num-banks: Specifies the number of interrupt banks (each of which can
14 - interrupt-controller: The presence of this property identifies the node
15 as an interrupt controller. No property value shall be defined.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
20 - #address-cells: Specifies the number of cells needed to encode an
22 'interrupt-map' nodes do not have to specify a parent unit address.
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| H A D | cdns,xtensa-pic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/interrupt-controller/cdns,xtensa-pic.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Max Filippov <jcmvbkbc@gmail.com>
15 Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX) and
16 Xtensa built-in Programmable Interrupt Controller (PIC)
21 - cdns,xtensa-mx
22 - cdns,xtensa-pic
24 '#interrupt-cells':
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | pci-msi.txt | 5 (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
6 Function number.
11 * Bits [15:8] are the Bus number.
12 * Bits [7:3] are the Device number.
13 * Bits [2:0] are the Function number.
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
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| H A D | ralink,rt3883-pci.txt | 1 * Mediatek/Ralink RT3883 PCI controller
7 - compatible: must be "ralink,rt3883-pci"
9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
23 - status: indicates the operational status of the device.
28 The main node must have two child nodes which describes the built-in
29 interrupt controller and the PCI host bridge.
31 a) Interrupt controller:
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| /freebsd/share/man/man4/ |
| H A D | ufshci.4 | 4 .\" SPDX-License-Identifier: BSD-2-Clause
15 .Nd Universal Flash Storage Host Controller Interface driver
19 .Bd -ragged -offset indent
25 .Bd -literal -offset indent
29 Universal Flash Storage (UFS) is a low-power, high-performance storage
30 standard composed of a host controller and a single target device.
33 .Bl -bullet
35 Initialization of the host controller and the target device
43 Operation in the legacy single-doorbell queue mode
48 After initialization, the controller is registered with the
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| H A D | bnxt.4 | 31 .Nd "Broadcom NetXtreme-C/NetXtreme-E Family Ethernet driver"
36 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
51 BCM57402/4/6, and BCM57502/4/8 Ethernet controller chips.
58 driver provides support for various NICs based on the Broadcom NetXtreme-C and
59 NetXtreme-E families of Gigabit Ethernet controller chip
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| /freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/ |
| H A D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
14 "BriefDescription": "read requests to memory controller",
25 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
36 "BriefDescription": "write requests to memory controller",
47 "BriefDescription": "Memory controller clock ticks",
55 "BriefDescription": "Pre-charge for reads",
65 "BriefDescription": "Pre-charge for writes",
81 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
92 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
97 "BriefDescription": "Number of DRAM Refreshes Issued",
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| /freebsd/share/doc/smm/02.config/ |
| H A D | 4.t | 80 \-DFUNNY \-DHAHA in the resultant makefile.
106 .IP "\fBtimezone\fP \fInumber\fP [ \fBdst\fP [ \fInumber\fP ] ]"
109 number of hours your timezone is west of GMT.
113 An optional integer or floating point number may be included
123 This is usually a cute name like ERNIE (short for Ernie Co-Vax) or
128 .IP "\fBmaxusers\fP \fInumber\fP"
130 The maximum expected number of simultaneously active user on this system is
131 .IR number .
132 This number is used to size several system data structures.
142 \fBconfig\fP\ \fIsysname\fP\ \fIconfig-clauses\fP
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | nvidia,tegra186-gpio.txt | 3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
4 controller. This binding document applies to both controllers. The register
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
11 package balls is under the control of a separate pin controller HW block. Two
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
36 The number of ports implemented by each GPIO controller varies. The number of
37 implemented GPIOs within each port varies. GPIO registers within a controller
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
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| H A D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
20 The Tegra186 GPIO controller allows software to set the IO direction of,
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| H A D | gpio.txt | 5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
42 The exact meaning of each specifier cell is controller specific, and must be
44 recommended to use the two-cell approach.
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| H A D | brcm,brcmstb-gpio.txt | 1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
14 the brcmstb GPIO controller registers
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
19 bit[0]: polarity (0 for active-high, 1 for active-low)
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| H A D | brcm,brcmstb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB "UPG GIO" GPIO controller
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
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| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | IdeControllerInit.h | 2 This file declares EFI IDE Controller Init Protocol
4 The EFI_IDE_CONTROLLER_INIT_PROTOCOL provides the chipset-specific information
6 IDE devices behind the controller are to be enumerated by a driver entity.
9 controller in a system. It is installed on the handle that corresponds to the
10 IDE controller. A driver entity that wishes to manage an IDE bus and possibly
12 instance that is associated with the controller to be managed.
14 A device handle for an IDE controller must contain an EFI_DEVICE_PATH_PROTOCOL.
16 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
17 SPDX-License-Identifier: BSD-2-Clause-Patent
44 /// The phase of the IDE Controller enumeration.
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| H A D | Usb2HostController.h | 3 The USB Host Controller Protocol is used by code, typically USB bus drivers,
7 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
58 /// if combines these two bitmaps into a 32-bit bitmap.
80 UINT8 TranslatorPortNumber; ///< the port number of the hub that device is connected to.
88 Retrieves the Host Controller capabilities.
91 @param MaxSpeed Host controller data transfer speed.
92 @param PortNumber Number of the root hub ports.
93 @param Is64BitCapable TRUE if controller supports 64-bit memory addressing,
96 @retval EFI_SUCCESS The host controller capabilities were retrieved successfully.
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| H A D | PciIo.h | 3 and DMA interfaces that a driver uses to access its PCI controller.
5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
49 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit de…
50 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater…
52 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit …
53 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x…
54 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F…
55 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x37…
62 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 By using a serial interface, the SIO controller significantly extend
14 the number of available GPIOs with a minimum number of additional
17 controller.
21 pattern: "^gpio@[0-9a-f]+$"
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| /freebsd/sys/dev/isci/scil/ |
| H A D | scic_library.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
90 * to the controller hardware. Completion of the request will occur
107 * @param[in] max_controller_count the maximum number of controllers that
120 * controller object creation/allocation.
123 * a controller.
137 * @param[in] max_controller_count the maximum number of controllers that
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| H A D | scif_library.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
81 * @param[in] max_controller_count the maximum number of controllers that
97 * @param[in] max_controller_count the maximum number of controllers that
108 * @brief This method will allocate the next available framework controller
115 * a controller.
117 * controller handle that was added to the library.
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| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | samsung-keypad.txt | 1 * Samsung's Keypad Controller device tree bindings
3 Samsung's Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
10 - compatible: should be one of the following
11 - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
12 controller.
13 - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
14 controller.
16 - reg: physical base address of the controller and length of memory mapped
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| /freebsd/stand/efi/include/ |
| H A D | efipciio.h | 3 and DMA interfaces that a driver uses to access its PCI controller.
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
9 http://opensource.org/licenses/bsd-license.php
56 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit dec…
57 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater …
59 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit d…
60 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
61 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7…
62 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377…
69 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
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| /freebsd/sys/dts/ |
| H A D | bindings-gpio.txt | 7 1.1 #gpio-cells
9 Property: #gpio-cells
13 Description: The #gpio-cells property defines the number of cells required
17 1.2 gpio-controller
19 Property: gpio-controller
23 Description: The presence of a gpio-controller property defines a node as a
24 GPIO controller node.
27 1.3 pin-count
29 Property: pin-count
33 Description: The pin-count property defines the number of GPIO pins.
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | qcom_nandc.txt | 1 * Qualcomm NAND controller
4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
11 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
13 * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
16 - reg: MMIO address range
17 - clocks: must contain core clock and always on clock
18 - clock-names: must contain "core" for the core clock and "aon" for the
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | cznic,turris-omnia-mcu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The MCU on Turris Omnia acts as a system controller providing additional
18 const: cznic,turris-omnia-mcu
27 interrupt-controller: true
29 '#interrupt-cells':
32 The first cell specifies the interrupt number (0 to 63), the second cell
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