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Searched +full:conf +full:- +full:mdio (Results 1 – 25 of 57) sorted by relevance

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/freebsd/sys/kern/
H A Dvfs_mountroot.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 1999-2004 Poul-Henning Kamp
43 #include <sys/conf.h>
158 sbuf_printf(&sb, "%s", h->who); in sysctl_vfs_root_mount_hold()
175 h->flags = RH_ALLOC; in root_mount_hold()
176 h->who = identifier; in root_mount_hold()
191 h->flags = RH_ARG; in root_mount_hold_token()
192 h->who = identifier; in root_mount_hold_token()
211 if (h == NULL || h->flags == RH_FREE) in root_mount_rel()
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sck-kv-g-revB.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-binding
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-binding
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H A Dzynqmp-sck-kv-g-revA.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
8 * "A" – A01 board un-modified (NXP)
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/net/ti-dp83867.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 /dts-v1/;
23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
24 #address-cells = <1>;
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-binding
113 mdio: mdio { global() label
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-binding
118 mdio: mdio { global() label
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H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-binding
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H A Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-cc
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-cc
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H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-binding
176 mdio: mdio { global() label
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H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-binding
216 mdio: mdio { global() label
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H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-binding
204 mdio: mdio { global() label
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986a-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
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H A Dmt7986a-bananapi-bpi-r3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-binding
194 mdio: mdio-bus { global() label
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H A Dmt7986b-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
20 stdout-path = "serial0:115200n8";
37 compatible = "mediatek,eth-mac";
39 phy-mode = "2500base-x";
41 fixed-link {
43 full-duplex;
48 mdio: mdio-bus { label
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H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r6
147 mdio: mdio-bus { global() label
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/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
42 phy-mode = "rgmii-id";
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H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
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/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_main.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 #include <dev/mdio/mdio.h>
79 { "qcom,ess-switch", 1 },
90 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in ar40xx_probe()
103 callout_reset(&sc->sc_phy_callout, hz, ar40xx_tick, sc); in ar40xx_tick()
119 return MDIO_READREG(sc->sc_mdio_dev, phy, reg); in ar40xx_readphy()
127 return MDIO_WRITEREG(sc->sc_mdio_dev, phy, reg, val); in ar40xx_writephy()
141 memset(&sc->sc_vlan, 0, sizeof(sc->sc_vlan)); in ar40xx_reset_switch()
145 sc->sc_vlan.vlan_id[i] = 0; in ar40xx_reset_switch()
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/freebsd/sys/dev/etherswitch/ip17x/
H A Dip17x.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2011-2012 Stefan Bethke.
56 #include <dev/mdio/mdio.h>
86 if (device_find_child(parent, "ip17x", -1) == NULL) in ip17x_identify()
123 sc->sc_switchtype = IP17X_SWITCH_IP175A; in ip17x_probe()
126 sc->sc_switchtype = IP17X_SWITCH_IP175C; in ip17x_probe()
138 sc->sc_switchtype = IP17X_SWITCH_IP175D; in ip17x_probe()
143 sc->sc_switchtype = IP17X_SWITCH_IP178C; in ip17x_probe()
146 sc->miipoll = 1; in ip17x_probe()
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/freebsd/sys/dev/etherswitch/infineon/
H A Dadm6996fc.c1 /*-
4 * Copyright (c) 2011-2012 Stefan Bethke.
34 * MDC/MDIO.
61 #include <dev/mdio/mdio.h>
107 mtx_lock(&(_sc)->sc_mtx)
109 mtx_unlock(&(_sc)->sc_mtx)
111 mtx_assert(&(_sc)->sc_mtx, (_what))
113 mtx_trylock(&(_sc)->sc_mtx)
156 device_set_desc(dev, "Infineon ADM6996FC/M/MX MDIO switch driver"); in adm6996fc_probe()
169 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->sc_dev)); in adm6996fc_attach_phys()
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/freebsd/sys/dev/etherswitch/felix/
H A Dfelix.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
148 felix_pci_ids, nitems(felix_pci_ids) - 1);
157 sc->dev = dev; in felix_probe()
159 for (id = felix_pci_ids; id->vendor != 0; ++id) { in felix_probe()
160 if (pci_get_device(dev) != id->device || in felix_probe()
161 pci_get_vendor(dev) != id->vendor) in felix_probe()
164 device_set_desc(dev, id->desc); in felix_probe()
179 device_printf(sc->dev, "Port node doesn't have reg property\n"); in felix_parse_port_fdt()
187 sc->ports[port].cpu_port = false; in felix_parse_port_fdt()
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/freebsd/sys/dev/etherswitch/mtkswitch/
H A Dmtkswitch.c1 /*-
3 * Copyright (c) 2011-2012 Stefan Bethke.
51 #include <dev/mdio/mdio.h>
75 { "ralink,rt3050-esw", MTK_SWITCH_RT3050 },
76 { "ralink,rt3352-esw", MTK_SWITCH_RT3352 },
77 { "ralink,rt5350-esw", MTK_SWITCH_RT5350 },
78 { "mediatek,mt7620-gsw", MTK_SWITCH_MT7620 },
79 { "mediatek,mt7621-gsw", MTK_SWITCH_MT7621 },
80 { "mediatek,mt7628-esw", MTK_SWITCH_MT7628 },
95 switch_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; in mtkswitch_probe()
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmediatek,mt7622-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt7622-pinctrl
19 - mediatek,mt7629-pinctrl
24 reg-names:
26 - const: eint
28 gpio-controller: true
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