Lines Matching +full:conf +full:- +full:mdio
1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 si5332_0: si5332-0 { /* u17 */
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <125000000>;
26 si5332_1: si5332-1 { /* u17 */
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <25000000>;
32 si5332_2: si5332-2 { /* u17 */
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <48000000>;
38 si5332_3: si5332-3 { /* u17 */
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <24000000>;
44 si5332_4: si5332-4 { /* u17 */
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <26000000>;
50 si5332_5: si5332-5 { /* u17 */
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <27000000>;
57 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
58 #address-cells = <1>;
59 #size-cells = <0>;
60 pinctrl-names = "default", "gpio";
61 pinctrl-0 = <&pinctrl_i2c1_default>;
62 pinctrl-1 = <&pinctrl_i2c1_gpio>;
63 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
64 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
66 /* u14 - 0x40 - ina260 */
67 /* u43 - 0x2d - usb5744 */
68 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
76 clock-names = "ref0", "ref1", "ref2";
81 phy-names = "dp-phy0", "dp-phy1";
83 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
88 assigned-clock-rates = <600000000>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_usb0_default>;
95 phy-names = "usb3-phy";
103 maximum-speed = "super-speed";
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_sdhci1_default>;
115 no-1-8-v;
116 disable-wp;
117 xlnx,mio-bank = <1>;
118 clk-phase-sd-hs = <126>, <60>;
119 clk-phase-uhs-sdr25 = <120>, <60>;
120 clk-phase-uhs-ddr50 = <126>, <48>;
121 assigned-clock-rates = <187498123>;
122 bus-width = <4>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_gem3_default>;
129 phy-handle = <&phy0>;
130 phy-mode = "rgmii-id";
131 assigned-clock-rates = <250000000>;
133 mdio: mdio {
134 #address-cells = <1>;
135 #size-cells = <0>;
137 phy0: ethernet-phy@1 {
138 #phy-cells = <1>;
140 compatible = "ethernet-phy-id2000.a231";
141 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
142 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
143 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
144 ti,dp83867-rxctrl-strap-quirk;
145 reset-assert-us = <100>;
146 reset-deassert-us = <280>;
147 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
155 pinctrl_uart1_default: uart1-default {
156 conf {
158 slew-rate = <SLEW_RATE_SLOW>;
159 power-source = <IO_STANDARD_LVCMOS18>;
160 drive-strength = <12>;
163 conf-rx {
165 bias-high-impedance;
168 conf-tx {
170 bias-disable;
179 pinctrl_i2c1_default: i2c1-default {
180 conf {
182 bias-pull-up;
183 slew-rate = <SLEW_RATE_SLOW>;
184 power-source = <IO_STANDARD_LVCMOS18>;
193 pinctrl_i2c1_gpio: i2c1-gpio {
194 conf {
196 slew-rate = <SLEW_RATE_SLOW>;
197 power-source = <IO_STANDARD_LVCMOS18>;
206 pinctrl_gem3_default: gem3-default {
207 conf {
209 slew-rate = <SLEW_RATE_SLOW>;
210 power-source = <IO_STANDARD_LVCMOS18>;
213 conf-rx {
215 bias-high-impedance;
216 low-power-disable;
219 conf-bootstrap {
221 bias-disable;
222 low-power-disable;
225 conf-tx {
228 bias-disable;
229 low-power-enable;
232 conf-mdio {
234 slew-rate = <SLEW_RATE_SLOW>;
235 power-source = <IO_STANDARD_LVCMOS18>;
236 bias-disable;
239 mux-mdio {
250 pinctrl_usb0_default: usb0-default {
251 conf {
253 power-source = <IO_STANDARD_LVCMOS18>;
256 conf-rx {
258 bias-high-impedance;
259 drive-strength = <12>;
260 slew-rate = <SLEW_RATE_FAST>;
263 conf-tx {
266 bias-disable;
267 drive-strength = <4>;
268 slew-rate = <SLEW_RATE_SLOW>;
277 pinctrl_sdhci1_default: sdhci1-default {
278 conf {
280 slew-rate = <SLEW_RATE_SLOW>;
281 power-source = <IO_STANDARD_LVCMOS18>;
282 bias-disable;
285 conf-cd {
287 bias-high-impedance;
288 bias-pull-up;
289 slew-rate = <SLEW_RATE_SLOW>;
290 power-source = <IO_STANDARD_LVCMOS18>;
293 mux-cd {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_uart1_default>;