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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-cc
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H A Dzynqmp-sck-kv-g-revB.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-binding
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/freebsd/sys/arm/allwinner/
H A Daw_rtc.c1 /*-
44 #include <dev/clk/clk_fixed.h>
65 #define IS_SUN7I (sc->conf->is_a20 == true)
92 #define RTC_READ(sc, reg) bus_read_4((sc)->res, (reg))
93 #define RTC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
133 { "allwinner,sun4i-a10-rtc", (uintptr_t) &a10_conf },
134 { "allwinner,sun7i-a20-rtc", (uintptr_t) &a20_conf },
135 { "allwinner,sun6i-a31-rtc", (uintptr_t) &a31_conf },
136 { "allwinner,sun8i-h3-rtc", (uintptr_t) &h3_conf },
137 { "allwinner,sun20i-d1-rtc", (uintptr_t) &h3_conf },
[all …]
H A Daw_gpio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
56 #include <dev/clk/clk.h>
277 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_gpio_conf},
280 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_gpio_conf},
283 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_gpio_conf},
286 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_gpio_conf},
289 {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_gpio_conf},
292 {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_gpio_conf},
295 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_gpio_conf},
[all …]
H A Da31_dmac.c1 /*-
49 #include <dev/clk/clk.h>
123 { "allwinner,sun6i-a31-dma", (uintptr_t)&a31_config },
124 { "allwinner,sun8i-a83t-dma", (uintptr_t)&a83t_config },
125 { "allwinner,sun8i-h3-dma", (uintptr_t)&h3_config },
126 { "allwinner,sun50i-a64-dma", (uintptr_t)&a64_config },
157 { -1, 0 }
160 #define DMA_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
161 #define DMA_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
172 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in a31dmac_probe()
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-suppl
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H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r6
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H A Dmt7986a-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
[all …]
H A Dmt7986a-bananapi-bpi-r3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-binding
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ul
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/freebsd/sys/dev/clk/
H A Dclk_mux.c1 /*-
28 #include <sys/conf.h>
35 #include <dev/clk/clk_mux.h>
50 static int clknode_mux_init(struct clknode *clk, device_t dev);
51 static int clknode_mux_set_mux(struct clknode *clk, int idx);
71 clknode_mux_init(struct clknode *clk, device_t dev) in clknode_mux_init() argument
77 sc = clknode_get_softc(clk); in clknode_mux_init()
79 DEVICE_LOCK(clk); in clknode_mux_init()
80 rv = RD4(clk, sc->offset, &reg); in clknode_mux_init()
81 DEVICE_UNLOCK(clk); in clknode_mux_init()
[all …]
H A Dclk_link.c1 /*-
28 #include <sys/conf.h>
40 #include <dev/clk/clk_link.h>
42 static int clknode_link_init(struct clknode *clk, device_t dev);
43 static int clknode_link_recalc(struct clknode *clk, uint64_t *freq);
44 static int clknode_link_set_freq(struct clknode *clk, uint64_t fin,
46 static int clknode_link_set_mux(struct clknode *clk, int idx);
47 static int clknode_link_set_gate(struct clknode *clk, bool enable);
62 clknode_link_init(struct clknode *clk, device_t dev) in clknode_link_init() argument
68 clknode_link_recalc(struct clknode *clk, uint64_t *freq) in clknode_link_recalc() argument
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H A Dclk_gate.c1 /*-
28 #include <sys/conf.h>
35 #include <dev/clk/clk_gate.h>
50 static int clknode_gate_init(struct clknode *clk, device_t dev);
51 static int clknode_gate_set_gate(struct clknode *clk, bool enable);
52 static int clknode_gate_get_gate(struct clknode *clk, bool *enable);
73 clknode_gate_init(struct clknode *clk, device_t dev) in clknode_gate_init() argument
76 clknode_init_parent_idx(clk, 0); in clknode_gate_init()
81 clknode_gate_set_gate(struct clknode *clk, bool enable) in clknode_gate_set_gate() argument
87 sc = clknode_get_softc(clk); in clknode_gate_set_gate()
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H A Dclk_div.c1 /*-
28 #include <sys/conf.h>
35 #include <dev/clk/clk_div.h>
50 static int clknode_div_init(struct clknode *clk, device_t dev);
51 static int clknode_div_recalc(struct clknode *clk, uint64_t *req);
86 if (!(sc->div_flags & CLK_DIV_WITH_TABLE)) in clknode_div_table_get_divider()
89 for (table = sc->div_table; table->divider != 0; table++) in clknode_div_table_get_divider()
90 if (table->value == sc->divider) in clknode_div_table_get_divider()
91 return (table->divider); in clknode_div_table_get_divider()
101 if (!(sc->div_flags & CLK_DIV_WITH_TABLE)) in clknode_div_table_get_value()
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H A Dclk_fixed.c1 /*-
30 #include <sys/conf.h>
47 #include <dev/clk/clk_fixed.h>
52 static int clknode_fixed_init(struct clknode *clk, device_t dev);
53 static int clknode_fixed_recalc(struct clknode *clk, uint64_t *freq);
54 static int clknode_fixed_set_freq(struct clknode *clk, uint64_t fin,
75 clknode_fixed_init(struct clknode *clk, device_t dev) in clknode_fixed_init() argument
79 sc = clknode_get_softc(clk); in clknode_fixed_init()
80 if (sc->freq == 0) in clknode_fixed_init()
81 clknode_init_parent_idx(clk, 0); in clknode_fixed_init()
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/freebsd/sys/arm64/freescale/imx/clk/
H A Dimx_clk_mux.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 #include <sys/conf.h>
37 #include <dev/clk/clk.h>
39 #include <arm64/freescale/imx/clk/imx_clk_mux.h>
54 static int imx_clk_mux_init(struct clknode *clk, device_t dev);
55 static int imx_clk_mux_set_mux(struct clknode *clk, int idx);
74 imx_clk_mux_init(struct clknode *clk, device_t dev) in imx_clk_mux_init() argument
80 sc = clknode_get_softc(clk); in imx_clk_mux_init()
82 DEVICE_LOCK(clk); in imx_clk_mux_init()
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/freebsd/sys/arm/ti/clk/
H A Dclock_common.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 #include <sys/conf.h>
41 #include <dev/clk/clk_mux.h>
54 read_clock_cells(device_t dev, struct clock_cell_info *clk) { in read_clock_cells() argument
63 clk->num_clock_cells = numbytes_clocks / sizeof(cell_t); in read_clock_cells()
69 clk->clock_cells = malloc(numbytes_clocks, M_DEVBUF, M_WAITOK|M_ZERO); in read_clock_cells()
70 clk->clock_cells_ncells = malloc(clk->num_clock_cells*sizeof(uint8_t), in read_clock_cells()
72 OF_getencprop(node, "clocks", clk->clock_cells, numbytes_clocks); in read_clock_cells()
75 clk->num_real_clocks = 0; in read_clock_cells()
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/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_rng.c61 #define RNG_JCLK_BYP_DIV_CNT 0x0000ff00 /* Jitter clk bypass divider
64 #define RNG_JCLK_BYP_SRC 0x00000020 /* Jitter clk bypass source */
65 #define RNG_JCLK_BYP_SEL 0x00000010 /* Jitter clk bypass select */
144 struct bcm_rng_conf const* conf; member
153 {"broadcom,bcm2835-rng", (uintptr_t)&bcm2835_rng_conf},
154 {"brcm,bcm2835-rng", (uintptr_t)&bcm2835_rng_conf},
156 {"brcm,bcm2711-rng200", (uintptr_t)&bcm2838_rng_conf},
157 {"brcm,bcm2838-rng", (uintptr_t)&bcm2838_rng_conf},
158 {"brcm,bcm2838-rng200", (uintptr_t)&bcm2838_rng_conf},
159 {"brcm,bcm7211-rng", (uintptr_t)&bcm2838_rng_conf},
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/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-ebaz4205.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
6 /include/ "zynq-7000.dtsi"
10 compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
28 ps-clk-frequency = <33333333>;
29 fclk-enable = <8>;
34 phy-mode = "mii";
35 phy-handle = <&phy>;
38 assigned-clocks = <&clkc 18>;
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H A Dzynq-microzed.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 /include/ "zynq-7000.dtsi"
11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
29 compatible = "usb-nop-xceiv";
30 #phy-cells = <0>;
35 ps-clk-frequency = <33333333>;
40 phy-mode = "rgmii-id";
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_mux.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 #include <sys/conf.h>
37 #include <dev/clk/clk.h>
40 #include <dev/clk/rockchip/rk_cru.h>
41 #include <dev/clk/rockchip/rk_clk_mux.h>
59 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
64 static int rk_clk_mux_init(struct clknode *clk, device_t dev);
65 static int rk_clk_mux_set_mux(struct clknode *clk, int idx);
66 static int rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent,
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
[all …]
/freebsd/sys/arm/ti/
H A Dti_spi.c1 /*-
78 int clk, conf, ctrl, div, i, j, wl; in ti_spi_printr() local
93 for (i = 0; i < sc->sc_numcs; i++) { in ti_spi_printr()
95 conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i)); in ti_spi_printr()
96 device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS); in ti_spi_printr()
97 if (conf & MCSPI_CONF_CLKG) { in ti_spi_printr()
98 div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; in ti_spi_printr()
102 j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; in ti_spi_printr()
103 while (j-- > 0) in ti_spi_printr()
106 clk = TI_SPI_GCLK / div; in ti_spi_printr()
[all …]
/freebsd/sys/arm/nvidia/
H A Dtegra_uart.c1 /*-
36 #include <sys/conf.h>
42 #include <dev/clk/clk.h>
56 * High-level UART interface.
60 clk_t clk; member
72 struct uart_bas *bas = &sc->sc_bas; in tegra_uart_attach()
78 ns8250->ier_rxbits = 0x1d; in tegra_uart_attach()
79 ns8250->ier_mask = 0xc0; in tegra_uart_attach()
80 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; in tegra_uart_attach()
81 ns8250->ier |= ns8250->ier_rxbits; in tegra_uart_attach()
[all …]

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