Lines Matching +full:conf +full:- +full:clk

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 /include/ "zynq-7000.dtsi"
11 	compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
25 		stdout-path = "serial0:115200n8";
29 		compatible = "usb-nop-xceiv";
30 		#phy-cells = <0>;
35 	ps-clk-frequency = <33333333>;
40 	phy-mode = "rgmii-id";
41 	phy-handle = <&ethernet_phy>;
43 	ethernet_phy: ethernet-phy@0 {
59 	usb-phy = <&usb_phy0>;
60 	pinctrl-names = "default";
61 	pinctrl-0 = <&pinctrl_usb0_default>;
65 	pinctrl_usb0_default: usb0-default {
71 		conf {
73 			slew-rate = <0>;
74 			io-standard = <1>;
77 		conf-rx {
79 			bias-high-impedance;
82 		conf-tx {
85 			bias-disable;