Lines Matching +full:conf +full:- +full:clk
1 /*-
78 int clk, conf, ctrl, div, i, j, wl; in ti_spi_printr() local
93 for (i = 0; i < sc->sc_numcs; i++) { in ti_spi_printr()
95 conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i)); in ti_spi_printr()
96 device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS); in ti_spi_printr()
97 if (conf & MCSPI_CONF_CLKG) { in ti_spi_printr()
98 div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; in ti_spi_printr()
102 j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; in ti_spi_printr()
103 while (j-- > 0) in ti_spi_printr()
106 clk = TI_SPI_GCLK / div; in ti_spi_printr()
107 wl = ((conf >> MCSPI_CONF_WL_SHIFT) & MCSPI_CONF_WL_MSK) + 1; in ti_spi_printr()
108 device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk); in ti_spi_printr()
121 uint32_t clkdiv, conf, div, extclk, reg; in ti_spi_set_clock() local
132 conf = clkdiv << MCSPI_CONF_CLK_SHIFT; in ti_spi_set_clock()
136 conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT; in ti_spi_set_clock()
146 TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf); in ti_spi_set_clock()
155 if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi")) in ti_spi_probe()
171 sc->sc_dev = dev; in ti_spi_attach()
181 if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs", in ti_spi_attach()
182 &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) { in ti_spi_attach()
183 sc->sc_numcs = 2; in ti_spi_attach()
187 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in ti_spi_attach()
189 if (!sc->sc_mem_res) { in ti_spi_attach()
194 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); in ti_spi_attach()
195 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); in ti_spi_attach()
198 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, in ti_spi_attach()
200 if (!sc->sc_irq_res) { in ti_spi_attach()
201 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); in ti_spi_attach()
207 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, in ti_spi_attach()
208 NULL, ti_spi_intr, sc, &sc->sc_intrhand)) { in ti_spi_attach()
209 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); in ti_spi_attach()
210 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); in ti_spi_attach()
215 mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF); in ti_spi_attach()
222 if (--timeout == 0) { in ti_spi_attach()
250 for (i = 0; i < sc->sc_numcs; i++) { in ti_spi_attach()
257 (8 - 1) << MCSPI_CONF_WL_SHIFT); in ti_spi_attach()
258 /* Set initial clock - 500kHz. */ in ti_spi_attach()
288 mtx_destroy(&sc->sc_mtx); in ti_spi_detach()
289 if (sc->sc_intrhand) in ti_spi_detach()
290 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); in ti_spi_detach()
291 if (sc->sc_irq_res) in ti_spi_detach()
292 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); in ti_spi_detach()
293 if (sc->sc_mem_res) in ti_spi_detach()
294 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); in ti_spi_detach()
307 cmd = sc->sc_cmd; in ti_spi_fill_fifo()
308 bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl); in ti_spi_fill_fifo()
309 while (bytes-- > 0) { in ti_spi_fill_fifo()
310 data = (uint8_t *)cmd->tx_cmd; in ti_spi_fill_fifo()
311 written = sc->sc_written++; in ti_spi_fill_fifo()
312 if (written >= cmd->tx_cmd_sz) { in ti_spi_fill_fifo()
313 data = (uint8_t *)cmd->tx_data; in ti_spi_fill_fifo()
314 written -= cmd->tx_cmd_sz; in ti_spi_fill_fifo()
316 if (sc->sc_fifolvl == 1) { in ti_spi_fill_fifo()
319 while (--timeout > 0 && (TI_SPI_READ(sc, in ti_spi_fill_fifo()
320 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) { in ti_spi_fill_fifo()
324 return (-1); in ti_spi_fill_fifo()
326 TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]); in ti_spi_fill_fifo()
340 cmd = sc->sc_cmd; in ti_spi_drain_fifo()
341 bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl); in ti_spi_drain_fifo()
342 while (bytes-- > 0) { in ti_spi_drain_fifo()
343 data = (uint8_t *)cmd->rx_cmd; in ti_spi_drain_fifo()
344 read = sc->sc_read++; in ti_spi_drain_fifo()
345 if (read >= cmd->rx_cmd_sz) { in ti_spi_drain_fifo()
346 data = (uint8_t *)cmd->rx_data; in ti_spi_drain_fifo()
347 read -= cmd->rx_cmd_sz; in ti_spi_drain_fifo()
349 if (sc->sc_fifolvl == 1) { in ti_spi_drain_fifo()
352 while (--timeout > 0 && (TI_SPI_READ(sc, in ti_spi_drain_fifo()
353 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) { in ti_spi_drain_fifo()
357 return (-1); in ti_spi_drain_fifo()
359 data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs)); in ti_spi_drain_fifo()
390 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { in ti_spi_intr()
391 sc->sc_flags |= TI_SPI_DONE; in ti_spi_intr()
392 wakeup(sc->sc_dev); in ti_spi_intr()
402 while (sc->sc_len - sc->sc_written > 0) { in ti_spi_pio_transfer()
403 if (ti_spi_fill_fifo(sc) == -1) in ti_spi_pio_transfer()
405 if (ti_spi_drain_fifo(sc) == -1) in ti_spi_pio_transfer()
434 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, in ti_spi_transfer()
436 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, in ti_spi_transfer()
446 if (cs > sc->sc_numcs) { in ti_spi_transfer()
462 while (sc->sc_flags & TI_SPI_BUSY) in ti_spi_transfer()
463 mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); in ti_spi_transfer()
466 sc->sc_flags = TI_SPI_BUSY; in ti_spi_transfer()
469 sc->sc_cs = cs; in ti_spi_transfer()
470 sc->sc_cmd = cmd; in ti_spi_transfer()
471 sc->sc_read = 0; in ti_spi_transfer()
472 sc->sc_written = 0; in ti_spi_transfer()
473 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; in ti_spi_transfer()
474 sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ); in ti_spi_transfer()
475 if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff) in ti_spi_transfer()
476 sc->sc_fifolvl = 1; /* FIFO disabled. */ in ti_spi_transfer()
478 sc->sc_fifolvl = 1; in ti_spi_transfer()
481 ti_spi_set_clock(sc, sc->sc_cs, clockhz); in ti_spi_transfer()
487 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); in ti_spi_transfer()
493 reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */ in ti_spi_transfer()
494 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); in ti_spi_transfer()
504 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); in ti_spi_transfer()
505 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE); in ti_spi_transfer()
508 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); in ti_spi_transfer()
509 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE); in ti_spi_transfer()
512 if (sc->sc_fifolvl == 1) in ti_spi_transfer()
516 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); in ti_spi_transfer()
518 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); in ti_spi_transfer()
527 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); in ti_spi_transfer()
529 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg); in ti_spi_transfer()
532 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); in ti_spi_transfer()
534 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); in ti_spi_transfer()
537 sc->sc_flags = 0; in ti_spi_transfer()