xref: /freebsd/sys/arm/nvidia/tegra_uart.c (revision 353e4c5a068d06b0d6dcfa9eb736ecb16e9eae45)
1ef2ee5d0SMichal Meloun /*-
2ef2ee5d0SMichal Meloun  * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3ef2ee5d0SMichal Meloun  * All rights reserved.
4ef2ee5d0SMichal Meloun  *
5ef2ee5d0SMichal Meloun  * Redistribution and use in source and binary forms, with or without
6ef2ee5d0SMichal Meloun  * modification, are permitted provided that the following conditions
7ef2ee5d0SMichal Meloun  * are met:
8ef2ee5d0SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
9ef2ee5d0SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
10ef2ee5d0SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
11ef2ee5d0SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
12ef2ee5d0SMichal Meloun  *    documentation and/or other materials provided with the distribution.
13ef2ee5d0SMichal Meloun  *
14ef2ee5d0SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15ef2ee5d0SMichal Meloun  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16ef2ee5d0SMichal Meloun  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17ef2ee5d0SMichal Meloun  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18ef2ee5d0SMichal Meloun  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19ef2ee5d0SMichal Meloun  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20ef2ee5d0SMichal Meloun  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21ef2ee5d0SMichal Meloun  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22ef2ee5d0SMichal Meloun  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23ef2ee5d0SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24ef2ee5d0SMichal Meloun  * SUCH DAMAGE.
25ef2ee5d0SMichal Meloun  */
26ef2ee5d0SMichal Meloun 
27ef2ee5d0SMichal Meloun #include <sys/cdefs.h>
28ef2ee5d0SMichal Meloun /*
29ef2ee5d0SMichal Meloun  * UART driver for Tegra SoCs.
30ef2ee5d0SMichal Meloun  */
31ef2ee5d0SMichal Meloun #include "opt_platform.h"
32ef2ee5d0SMichal Meloun 
33ef2ee5d0SMichal Meloun #include <sys/param.h>
34ef2ee5d0SMichal Meloun #include <sys/systm.h>
35ef2ee5d0SMichal Meloun #include <sys/bus.h>
36ef2ee5d0SMichal Meloun #include <sys/conf.h>
37ef2ee5d0SMichal Meloun #include <sys/kernel.h>
38ef2ee5d0SMichal Meloun #include <sys/module.h>
39ef2ee5d0SMichal Meloun #include <sys/sysctl.h>
40ef2ee5d0SMichal Meloun #include <machine/bus.h>
41ef2ee5d0SMichal Meloun 
42be82b3a0SEmmanuel Vadot #include <dev/clk/clk.h>
431f469a9fSEmmanuel Vadot #include <dev/hwreset/hwreset.h>
44ef2ee5d0SMichal Meloun #include <dev/ofw/ofw_bus.h>
45ef2ee5d0SMichal Meloun #include <dev/ofw/ofw_bus_subr.h>
46ef2ee5d0SMichal Meloun #include <dev/uart/uart.h>
47ef2ee5d0SMichal Meloun #include <dev/uart/uart_cpu.h>
48ef2ee5d0SMichal Meloun #include <dev/uart/uart_cpu_fdt.h>
49ef2ee5d0SMichal Meloun #include <dev/uart/uart_bus.h>
50ef2ee5d0SMichal Meloun #include <dev/uart/uart_dev_ns8250.h>
51ef2ee5d0SMichal Meloun #include <dev/ic/ns16550.h>
52ef2ee5d0SMichal Meloun 
53ef2ee5d0SMichal Meloun #include "uart_if.h"
54ef2ee5d0SMichal Meloun 
55ef2ee5d0SMichal Meloun /*
56ef2ee5d0SMichal Meloun  * High-level UART interface.
57ef2ee5d0SMichal Meloun  */
58ef2ee5d0SMichal Meloun struct tegra_softc {
59ef2ee5d0SMichal Meloun 	struct ns8250_softc 	ns8250_base;
60ef2ee5d0SMichal Meloun 	clk_t			clk;
61ef2ee5d0SMichal Meloun 	hwreset_t		reset;
62ef2ee5d0SMichal Meloun };
63ef2ee5d0SMichal Meloun 
64ef2ee5d0SMichal Meloun /*
65ef2ee5d0SMichal Meloun  * UART class interface.
66ef2ee5d0SMichal Meloun  */
67ef2ee5d0SMichal Meloun static int
tegra_uart_attach(struct uart_softc * sc)68ef2ee5d0SMichal Meloun tegra_uart_attach(struct uart_softc *sc)
69ef2ee5d0SMichal Meloun {
70ef2ee5d0SMichal Meloun 	int rv;
71ef2ee5d0SMichal Meloun 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
72ef2ee5d0SMichal Meloun 	struct uart_bas *bas = &sc->sc_bas;
73ef2ee5d0SMichal Meloun 
74ef2ee5d0SMichal Meloun 	rv = ns8250_bus_attach(sc);
75ef2ee5d0SMichal Meloun 	if (rv != 0)
76ef2ee5d0SMichal Meloun 		return (rv);
77ef2ee5d0SMichal Meloun 
78ef2ee5d0SMichal Meloun 	ns8250->ier_rxbits = 0x1d;
79ef2ee5d0SMichal Meloun 	ns8250->ier_mask = 0xc0;
80ef2ee5d0SMichal Meloun 	ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
8158872fc0SMichal Meloun 	ns8250->ier |= ns8250->ier_rxbits;
82ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_IER, ns8250->ier);
83ef2ee5d0SMichal Meloun 	uart_barrier(bas);
84ef2ee5d0SMichal Meloun 	return (0);
85ef2ee5d0SMichal Meloun }
86ef2ee5d0SMichal Meloun 
87ef2ee5d0SMichal Meloun static void
tegra_uart_grab(struct uart_softc * sc)88ef2ee5d0SMichal Meloun tegra_uart_grab(struct uart_softc *sc)
89ef2ee5d0SMichal Meloun {
90ef2ee5d0SMichal Meloun 	struct uart_bas *bas = &sc->sc_bas;
91ef2ee5d0SMichal Meloun 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
92ef2ee5d0SMichal Meloun 	u_char ier;
93ef2ee5d0SMichal Meloun 
94ef2ee5d0SMichal Meloun 	/*
95ef2ee5d0SMichal Meloun 	 * turn off all interrupts to enter polling mode. Leave the
96ef2ee5d0SMichal Meloun 	 * saved mask alone. We'll restore whatever it was in ungrab.
97ef2ee5d0SMichal Meloun 	 * All pending interrupt signals are reset when IER is set to 0.
98ef2ee5d0SMichal Meloun 	 */
99ef2ee5d0SMichal Meloun 	uart_lock(sc->sc_hwmtx);
100ef2ee5d0SMichal Meloun 	ier = uart_getreg(bas, REG_IER);
101ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_IER, ier & ns8250->ier_mask);
1023e13ea16SMichal Meloun 
1033e13ea16SMichal Meloun 	while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0)
1043e13ea16SMichal Meloun 		;
1053e13ea16SMichal Meloun 
106ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_FCR, 0);
107ef2ee5d0SMichal Meloun 	uart_barrier(bas);
108ef2ee5d0SMichal Meloun 	uart_unlock(sc->sc_hwmtx);
109ef2ee5d0SMichal Meloun }
110ef2ee5d0SMichal Meloun 
111ef2ee5d0SMichal Meloun static void
tegra_uart_ungrab(struct uart_softc * sc)112ef2ee5d0SMichal Meloun tegra_uart_ungrab(struct uart_softc *sc)
113ef2ee5d0SMichal Meloun {
114ef2ee5d0SMichal Meloun 	struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
115ef2ee5d0SMichal Meloun 	struct uart_bas *bas = &sc->sc_bas;
116ef2ee5d0SMichal Meloun 
117ef2ee5d0SMichal Meloun 	/*
118ef2ee5d0SMichal Meloun 	 * Restore previous interrupt mask
119ef2ee5d0SMichal Meloun 	 */
120ef2ee5d0SMichal Meloun 	uart_lock(sc->sc_hwmtx);
121ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_FCR, ns8250->fcr);
122ef2ee5d0SMichal Meloun 	uart_setreg(bas, REG_IER, ns8250->ier);
123ef2ee5d0SMichal Meloun 	uart_barrier(bas);
124ef2ee5d0SMichal Meloun 	uart_unlock(sc->sc_hwmtx);
125ef2ee5d0SMichal Meloun }
126ef2ee5d0SMichal Meloun 
127ef2ee5d0SMichal Meloun static kobj_method_t tegra_methods[] = {
128ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_probe,		ns8250_bus_probe),
129ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_attach,		tegra_uart_attach),
130ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_detach,		ns8250_bus_detach),
131ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_flush,		ns8250_bus_flush),
132ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_getsig,		ns8250_bus_getsig),
133ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_ioctl,		ns8250_bus_ioctl),
134ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_ipend,		ns8250_bus_ipend),
135ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_param,		ns8250_bus_param),
136ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_receive,	ns8250_bus_receive),
137ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_setsig,		ns8250_bus_setsig),
138ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_transmit,	ns8250_bus_transmit),
139*353e4c5aSMarius Strobl 	KOBJMETHOD(uart_txbusy,		ns8250_bus_txbusy),
140ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_grab,		tegra_uart_grab),
141ef2ee5d0SMichal Meloun 	KOBJMETHOD(uart_ungrab,		tegra_uart_ungrab),
142ef2ee5d0SMichal Meloun 	KOBJMETHOD_END
143ef2ee5d0SMichal Meloun };
144ef2ee5d0SMichal Meloun 
145ef2ee5d0SMichal Meloun static struct uart_class tegra_uart_class = {
146ef2ee5d0SMichal Meloun 	"tegra class",
147ef2ee5d0SMichal Meloun 	tegra_methods,
148ef2ee5d0SMichal Meloun 	sizeof(struct tegra_softc),
149ef2ee5d0SMichal Meloun 	.uc_ops = &uart_ns8250_ops,
150ef2ee5d0SMichal Meloun 	.uc_range = 8,
151ef2ee5d0SMichal Meloun 	.uc_rclk = 0,
152ef2ee5d0SMichal Meloun };
153ef2ee5d0SMichal Meloun 
154ef2ee5d0SMichal Meloun /* Compatible devices. */
155ef2ee5d0SMichal Meloun static struct ofw_compat_data compat_data[] = {
156ef2ee5d0SMichal Meloun 	{"nvidia,tegra124-uart", (uintptr_t)&tegra_uart_class},
157b9cbd68dSMichal Meloun 	{"nvidia,tegra210-uart", (uintptr_t)&tegra_uart_class},
158ef2ee5d0SMichal Meloun 	{NULL,			 (uintptr_t)NULL},
159ef2ee5d0SMichal Meloun };
160ef2ee5d0SMichal Meloun 
161ef2ee5d0SMichal Meloun UART_FDT_CLASS(compat_data);
162ef2ee5d0SMichal Meloun 
163ef2ee5d0SMichal Meloun /*
164ef2ee5d0SMichal Meloun  * UART Driver interface.
165ef2ee5d0SMichal Meloun  */
166ef2ee5d0SMichal Meloun static int
uart_fdt_get_shift1(phandle_t node)167ef2ee5d0SMichal Meloun uart_fdt_get_shift1(phandle_t node)
168ef2ee5d0SMichal Meloun {
169ef2ee5d0SMichal Meloun 	pcell_t shift;
170ef2ee5d0SMichal Meloun 
171ef2ee5d0SMichal Meloun 	if ((OF_getencprop(node, "reg-shift", &shift, sizeof(shift))) <= 0)
172ef2ee5d0SMichal Meloun 		shift = 2;
173ef2ee5d0SMichal Meloun 	return ((int)shift);
174ef2ee5d0SMichal Meloun }
175ef2ee5d0SMichal Meloun 
176ef2ee5d0SMichal Meloun static int
tegra_uart_probe(device_t dev)177ef2ee5d0SMichal Meloun tegra_uart_probe(device_t dev)
178ef2ee5d0SMichal Meloun {
179ef2ee5d0SMichal Meloun 	struct tegra_softc *sc;
180ef2ee5d0SMichal Meloun 	phandle_t node;
181ef2ee5d0SMichal Meloun 	uint64_t freq;
182ef2ee5d0SMichal Meloun 	int shift;
183ef2ee5d0SMichal Meloun 	int rv;
184ef2ee5d0SMichal Meloun 	const struct ofw_compat_data *cd;
185ef2ee5d0SMichal Meloun 
186ef2ee5d0SMichal Meloun 	sc = device_get_softc(dev);
187ef2ee5d0SMichal Meloun 	if (!ofw_bus_status_okay(dev))
188ef2ee5d0SMichal Meloun 		return (ENXIO);
189ef2ee5d0SMichal Meloun 	cd = ofw_bus_search_compatible(dev, compat_data);
190ef2ee5d0SMichal Meloun 	if (cd->ocd_data == 0)
191ef2ee5d0SMichal Meloun 		return (ENXIO);
192ef2ee5d0SMichal Meloun 	sc->ns8250_base.base.sc_class = (struct uart_class *)cd->ocd_data;
193dac93553SMichal Meloun 	rv = hwreset_get_by_ofw_name(dev, 0, "serial", &sc->reset);
194ef2ee5d0SMichal Meloun 	if (rv != 0) {
195ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot get 'serial' reset\n");
196ef2ee5d0SMichal Meloun 		return (ENXIO);
197ef2ee5d0SMichal Meloun 	}
198ef2ee5d0SMichal Meloun 	rv = hwreset_deassert(sc->reset);
199ef2ee5d0SMichal Meloun 	if (rv != 0) {
200ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot unreset 'serial' reset\n");
201ef2ee5d0SMichal Meloun 		return (ENXIO);
202ef2ee5d0SMichal Meloun 	}
203ef2ee5d0SMichal Meloun 	node = ofw_bus_get_node(dev);
204ef2ee5d0SMichal Meloun 	shift = uart_fdt_get_shift1(node);
205dac93553SMichal Meloun 	rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
206ef2ee5d0SMichal Meloun 	if (rv != 0) {
207ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot get UART clock: %d\n", rv);
208ef2ee5d0SMichal Meloun 		return (ENXIO);
209ef2ee5d0SMichal Meloun 	}
210ef2ee5d0SMichal Meloun 	rv = clk_enable(sc->clk);
211ef2ee5d0SMichal Meloun 	if (rv != 0) {
212ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot enable UART clock: %d\n", rv);
213ef2ee5d0SMichal Meloun 		return (ENXIO);
214ef2ee5d0SMichal Meloun 	}
215ef2ee5d0SMichal Meloun 	rv = clk_get_freq(sc->clk, &freq);
216ef2ee5d0SMichal Meloun 	if (rv != 0) {
217ef2ee5d0SMichal Meloun 		device_printf(dev, "Cannot enable UART clock: %d\n", rv);
218ef2ee5d0SMichal Meloun 		return (ENXIO);
219ef2ee5d0SMichal Meloun 	}
220381388b9SMatt Macy 	return (uart_bus_probe(dev, shift, 0, (int)freq, 0, 0, 0));
221ef2ee5d0SMichal Meloun }
222ef2ee5d0SMichal Meloun 
223ef2ee5d0SMichal Meloun static int
tegra_uart_detach(device_t dev)224ef2ee5d0SMichal Meloun tegra_uart_detach(device_t dev)
225ef2ee5d0SMichal Meloun {
226ef2ee5d0SMichal Meloun 	struct tegra_softc *sc;
227ef2ee5d0SMichal Meloun 
228ef2ee5d0SMichal Meloun 	sc = device_get_softc(dev);
229ef2ee5d0SMichal Meloun 	if (sc->clk != NULL) {
230ef2ee5d0SMichal Meloun 		clk_release(sc->clk);
231ef2ee5d0SMichal Meloun 	}
232ef2ee5d0SMichal Meloun 
233ef2ee5d0SMichal Meloun 	return (uart_bus_detach(dev));
234ef2ee5d0SMichal Meloun }
235ef2ee5d0SMichal Meloun 
236ef2ee5d0SMichal Meloun static device_method_t tegra_uart_bus_methods[] = {
237ef2ee5d0SMichal Meloun 	/* Device interface */
238ef2ee5d0SMichal Meloun 	DEVMETHOD(device_probe,		tegra_uart_probe),
239ef2ee5d0SMichal Meloun 	DEVMETHOD(device_attach,	uart_bus_attach),
240ef2ee5d0SMichal Meloun 	DEVMETHOD(device_detach,	tegra_uart_detach),
241*353e4c5aSMarius Strobl 	DEVMETHOD_END
242ef2ee5d0SMichal Meloun };
243ef2ee5d0SMichal Meloun 
244ef2ee5d0SMichal Meloun static driver_t tegra_uart_driver = {
245ef2ee5d0SMichal Meloun 	uart_driver_name,
246ef2ee5d0SMichal Meloun 	tegra_uart_bus_methods,
247ef2ee5d0SMichal Meloun 	sizeof(struct tegra_softc),
248ef2ee5d0SMichal Meloun };
249ef2ee5d0SMichal Meloun 
250c90ea831SJohn Baldwin DRIVER_MODULE(tegra_uart, simplebus,  tegra_uart_driver, 0, 0);
251