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/linux/drivers/perf/
H A Darm-cmn.c3 // ARM CMN/CI interconnect PMU driver
243 /* CMN-600 r0px shouldn't exist in silicon, thankfully */
407 static int arm_cmn_xyidbits(const struct arm_cmn *cmn) in arm_cmn_xyidbits() argument
409 return fls((cmn->mesh_x - 1) | (cmn->mesh_y - 1)); in arm_cmn_xyidbits()
421 static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn, in arm_cmn_node_to_xp() argument
425 int bits = arm_cmn_xyidbits(cmn); in arm_cmn_node_to_xp()
429 return cmn->xps + cmn->mesh_x * y + x; in arm_cmn_node_to_xp()
431 static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn, in arm_cmn_node() argument
436 for (dn = cmn->dns; dn->type; dn++) in arm_cmn_node()
442 static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn) in arm_cmn_model() argument
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq9574-cmn-pll.yaml4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
7 title: Qualcomm CMN PLL Clock Controller on IPQ SoC
14 The CMN (or common) PLL clock controller expects a reference
16 The CMN PLL supplies a number of fixed rate output clocks to
19 and the externally connected switch or PHY devices. The CMN
27 - qcom,ipq5018-cmn-pll
28 - qcom,ipq5332-cmn-pll
29 - qcom,ipq5424-cmn-pll
30 - qcom,ipq6018-cmn-pll
31 - qcom,ipq8074-cmn-pll
[all …]
/linux/drivers/clk/qcom/
H A Dipq-cmn-pll.c7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
21 * clocks from CMN PLL on IPQ5424 are the same as IPQ9574.
23 * On the IPQ5332 SoC, the CMN PLL provides a single 50 MHZ clock output to
37 * | CMN PLL block |
56 #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
57 #include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
58 #include <dt-bindings/clock/qcom,ipq5332-cmn-pll.h>
59 #include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
[all …]
H A DKconfig508 tristate "IPQ CMN PLL Clock Controller"
512 Support for CMN PLL clock controller on IPQ platform. The
513 CMN PLL consumes the AHB/SYS clocks from GCC and supplies
515 Say Y or M if you want to support CMN PLL clock on the IPQ
630 NSSCC receives the clock sources from GCC, CMN PLL and UNIPHY (PCS).
/linux/Documentation/devicetree/bindings/perf/
H A Darm,cmn.yaml5 $id: http://devicetree.org/schemas/perf/arm,cmn.yaml#
8 title: Arm CMN (Coherent Mesh Network) Performance Monitors
16 - arm,cmn-600
17 - arm,cmn-650
18 - arm,cmn-700
19 - arm,cmn-s3
39 description: Offset from PERIPHBASE of CMN-600's configuration
41 relevant for newer CMN/CI products.
52 const: arm,cmn-600
64 compatible = "arm,cmn-600";
/linux/tools/perf/pmu-events/arch/arm64/arm/cmn/sys/
H A Dmetric.json5 "MetricGroup": "cmn",
14 "MetricGroup": "cmn",
23 "MetricGroup": "cmn",
32 "MetricGroup": "cmn",
41 "MetricGroup": "cmn",
50 "MetricGroup": "cmn",
59 "MetricGroup": "cmn",
68 "MetricGroup": "cmn",
/linux/Documentation/admin-guide/perf/
H A Darm-cmn.rst5 CMN-600 is a configurable mesh interconnect consisting of a rectangular
9 CMN implements a distributed PMU design as part of its debug and trace
21 more than one CMN together via external CCIX links - in this situation,
44 "nodeid" to the appropriate value derived from the CMN configuration
/linux/include/dt-bindings/clock/
H A Dqcom,ipq5332-cmn-pll.h9 /* CMN PLL core clock. */
12 /* The output clocks from CMN PLL of IPQ5332. */
/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml45 - const: cmn
147 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
/linux/drivers/net/ethernet/broadcom/
H A Dbgmac-bcma.c82 bcma_maskset32(bgmac->bcma.cmn, offset, mask, set); in bcma_bgmac_cmn_maskset32()
171 dev_err(bgmac->dev, "GMAC CMN core not found (required for BCM4706)\n"); in bgmac_probe()
175 bgmac->bcma.cmn = core->bus->drv_gmac_cmn.core; in bgmac_probe()
H A Dbgmac.h448 /* Reference to CMN core for BCM4706 */
449 struct bcma_device *cmn; member
/linux/arch/arm/lib/
H A Dmemmove.S75 PLD( cmn r2, #96 )
175 PLD( cmn r2, #96 )
H A Dcopy_template.S109 PLD( cmn r2, #96 )
225 PLD( cmn r2, #96 )
H A Dlib1funcs.S193 2: cmn \order, #2
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dmemory.json12 …on": "Counts accesses to another chip, which is implemented as a different CMN mesh in the system.…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dmemory.json12 …on": "Counts accesses to another chip, which is implemented as a different CMN mesh in the system.…
/linux/arch/arm/probes/kprobes/
H A Dtest-thumb.c107 DATA_PROCESSING16("cmn",0xf00f00ff) in kprobe_thumb16_test_cases()
533 DATA_PROCESSING32_NM("cmn",VAL2) in kprobe_thumb32_test_cases()
559 TEST_UNSUPPORTED(__inst_thumb32(0xeb170f0d) " @ cmn.w r7, sp") in kprobe_thumb32_test_cases()
560 TEST_UNSUPPORTED(__inst_thumb32(0xeb170f0f) " @ cmn.w r7, pc") in kprobe_thumb32_test_cases()
561 TEST_P("cmn.w sp, r",7,0,"") in kprobe_thumb32_test_cases()
562 TEST_UNSUPPORTED(__inst_thumb32(0xeb1f0f07) " @ cmn.w pc, r7") in kprobe_thumb32_test_cases()
563 TEST( "cmn sp, #0x00080008") in kprobe_thumb32_test_cases()
564 TEST_UNSUPPORTED(__inst_thumb32(0xf11f1f08) " @ cmn pc, #0x00080008") in kprobe_thumb32_test_cases()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c39 /* PMA CMN Registers */
747 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); in rk_udphy_status_check()
834 /* Step 5: deassert cmn/lane rstn */ in rk_udphy_init()
836 rk_udphy_reset_deassert(udphy, "cmn"); in rk_udphy_init()
1554 "init", "cmn", "lane", "pcs_apb", "pma_apb"
/linux/drivers/net/wireless/ath/ath12k/wifi7/
H A Ddp_mon.c525 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn(const struct hal_mon_usig_cmn *cmn, in ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn() argument
530 ppdu_info->u_sig_info.bw = le32_get_bits(cmn->info0, in ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn()
532 ppdu_info->u_sig_info.ul_dl = le32_get_bits(cmn->info0, in ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn()
541 ATH12K_LE32_DEC_ENC(cmn->info0, in ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn()
548 ATH12K_LE32_DEC_ENC(cmn->info0, in ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn()
551 ATH12K_LE32_DEC_ENC(cmn->info0, in ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn()
705 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn(&usig->cmn, ppdu_info); in ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_hdr()
/linux/arch/arm/probes/
H A Ddecode-arm.c310 /* CMN (register) cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */
335 /* CMN (reg-shift reg) cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
387 /* CMN (immediate) cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx */
H A Ddecode-thumb.c81 /* CMN 1110 1011 0001 xxxx xxxx 1111 xxxx xxxx */
141 /* CMN 1111 0x01 0001 xxxx 0xxx 1111 xxxx xxxx */
726 /* CMN (register) 0100 0010 11xx xxxx */
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u.dtsi107 reset-names = "presetn", "cmn-rstb";
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_sspp_v13.c12 /* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */
/linux/arch/arm/kernel/
H A Dphys2virt.S58 cmn r0, #1
/linux/tools/perf/pmu-events/
H A DBuild81 ARMS := $(shell ls -d pmu-events/arch/arm64/arm/*|grep -v cmn)

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