1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #include "hal_desc.h"
8 #include "../dp_mon.h"
9 #include "dp_mon.h"
10 #include "../debug.h"
11 #include "hal_qcn9274.h"
12 #include "dp_rx.h"
13 #include "../dp_tx.h"
14 #include "../peer.h"
15
16 static void
ath12k_wifi7_dp_mon_hal_aggr_tlv(struct hal_rx_mon_ppdu_info * ppdu_info,u16 tlv_len,const void * tlv_data)17 ath12k_wifi7_dp_mon_hal_aggr_tlv(struct hal_rx_mon_ppdu_info *ppdu_info,
18 u16 tlv_len, const void *tlv_data)
19 {
20 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) {
21 memcpy(ppdu_info->tlv_aggr.buf + ppdu_info->tlv_aggr.cur_len,
22 tlv_data, tlv_len);
23 ppdu_info->tlv_aggr.cur_len += tlv_len;
24 }
25 }
26
27 static void
ath12k_wifi7_dp_mon_rx_memset_ppdu_info(struct hal_rx_mon_ppdu_info * ppdu_info)28 ath12k_wifi7_dp_mon_rx_memset_ppdu_info(struct hal_rx_mon_ppdu_info *ppdu_info)
29 {
30 memset(ppdu_info, 0, sizeof(*ppdu_info));
31 ppdu_info->peer_id = HAL_INVALID_PEERID;
32 }
33
34 /* Hardware fill buffer with 128 bytes aligned. So need to reap it
35 * with 128 bytes aligned.
36 */
37 #define RXDMA_DATA_DMA_BLOCK_SIZE 128
38
39 static void
ath12k_wifi7_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info * info,bool * is_frag,u32 * total_len,u32 * frag_len,u32 * msdu_cnt)40 ath12k_wifi7_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
41 bool *is_frag, u32 *total_len,
42 u32 *frag_len, u32 *msdu_cnt)
43 {
44 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
45 *is_frag = true;
46 *frag_len = (RX_MON_STATUS_BASE_BUF_SIZE -
47 sizeof(struct hal_rx_desc)) &
48 ~(RXDMA_DATA_DMA_BLOCK_SIZE - 1);
49 *total_len += *frag_len;
50 } else {
51 if (*is_frag)
52 *frag_len = info->msdu_len - *total_len;
53 else
54 *frag_len = info->msdu_len;
55
56 *msdu_cnt -= 1;
57 }
58 }
59
60 static void
ath12k_wifi7_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats * ppdu_end_user,struct hal_rx_user_status * rx_user_status)61 ath12k_wifi7_dp_mon_rx_handle_ofdma_info(const struct hal_rx_ppdu_end_user_stats *ppdu_end_user,
62 struct hal_rx_user_status *rx_user_status)
63 {
64 rx_user_status->ul_ofdma_user_v0_word0 =
65 __le32_to_cpu(ppdu_end_user->usr_resp_ref);
66 rx_user_status->ul_ofdma_user_v0_word1 =
67 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext);
68 }
69
70 static void
ath12k_wifi7_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats * stats,void * ppduinfo,struct hal_rx_user_status * rx_user_status)71 ath12k_wifi7_dp_mon_rx_populate_byte_count(const struct hal_rx_ppdu_end_user_stats *stats,
72 void *ppduinfo,
73 struct hal_rx_user_status *rx_user_status)
74 {
75 rx_user_status->mpdu_ok_byte_count =
76 le32_get_bits(stats->info7,
77 HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT);
78 rx_user_status->mpdu_err_byte_count =
79 le32_get_bits(stats->info8,
80 HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT);
81 }
82
83 static void
ath12k_wifi7_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats * rx_tlv,struct hal_rx_mon_ppdu_info * ppdu_info,struct hal_rx_user_status * rx_user_status)84 ath12k_wifi7_dp_mon_rx_populate_mu_user_info(const struct hal_rx_ppdu_end_user_stats *rx_tlv,
85 struct hal_rx_mon_ppdu_info *ppdu_info,
86 struct hal_rx_user_status *rx_user_status)
87 {
88 rx_user_status->ast_index = ppdu_info->ast_index;
89 rx_user_status->tid = ppdu_info->tid;
90 rx_user_status->tcp_ack_msdu_count =
91 ppdu_info->tcp_ack_msdu_count;
92 rx_user_status->tcp_msdu_count =
93 ppdu_info->tcp_msdu_count;
94 rx_user_status->udp_msdu_count =
95 ppdu_info->udp_msdu_count;
96 rx_user_status->other_msdu_count =
97 ppdu_info->other_msdu_count;
98 rx_user_status->frame_control = ppdu_info->frame_control;
99 rx_user_status->frame_control_info_valid =
100 ppdu_info->frame_control_info_valid;
101 rx_user_status->data_sequence_control_info_valid =
102 ppdu_info->data_sequence_control_info_valid;
103 rx_user_status->first_data_seq_ctrl =
104 ppdu_info->first_data_seq_ctrl;
105 rx_user_status->preamble_type = ppdu_info->preamble_type;
106 rx_user_status->ht_flags = ppdu_info->ht_flags;
107 rx_user_status->vht_flags = ppdu_info->vht_flags;
108 rx_user_status->he_flags = ppdu_info->he_flags;
109 rx_user_status->rs_flags = ppdu_info->rs_flags;
110
111 rx_user_status->mpdu_cnt_fcs_ok =
112 ppdu_info->num_mpdu_fcs_ok;
113 rx_user_status->mpdu_cnt_fcs_err =
114 ppdu_info->num_mpdu_fcs_err;
115 memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0],
116 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
117 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
118
119 ath12k_wifi7_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status);
120 }
121
122 static inline enum ath12k_eht_ru_size
hal_rx_mon_hal_ru_size_to_ath12k_ru_size(u32 hal_ru_size)123 hal_rx_mon_hal_ru_size_to_ath12k_ru_size(u32 hal_ru_size)
124 {
125 switch (hal_ru_size) {
126 case HAL_EHT_RU_26:
127 return ATH12K_EHT_RU_26;
128 case HAL_EHT_RU_52:
129 return ATH12K_EHT_RU_52;
130 case HAL_EHT_RU_78:
131 return ATH12K_EHT_RU_52_26;
132 case HAL_EHT_RU_106:
133 return ATH12K_EHT_RU_106;
134 case HAL_EHT_RU_132:
135 return ATH12K_EHT_RU_106_26;
136 case HAL_EHT_RU_242:
137 return ATH12K_EHT_RU_242;
138 case HAL_EHT_RU_484:
139 return ATH12K_EHT_RU_484;
140 case HAL_EHT_RU_726:
141 return ATH12K_EHT_RU_484_242;
142 case HAL_EHT_RU_996:
143 return ATH12K_EHT_RU_996;
144 case HAL_EHT_RU_996x2:
145 return ATH12K_EHT_RU_996x2;
146 case HAL_EHT_RU_996x3:
147 return ATH12K_EHT_RU_996x3;
148 case HAL_EHT_RU_996x4:
149 return ATH12K_EHT_RU_996x4;
150 case HAL_EHT_RU_NONE:
151 return ATH12K_EHT_RU_INVALID;
152 case HAL_EHT_RU_996_484:
153 return ATH12K_EHT_RU_996_484;
154 case HAL_EHT_RU_996x2_484:
155 return ATH12K_EHT_RU_996x2_484;
156 case HAL_EHT_RU_996x3_484:
157 return ATH12K_EHT_RU_996x3_484;
158 case HAL_EHT_RU_996_484_242:
159 return ATH12K_EHT_RU_996_484_242;
160 default:
161 return ATH12K_EHT_RU_INVALID;
162 }
163 }
164
165 static inline u32
hal_rx_ul_ofdma_ru_size_to_width(enum ath12k_eht_ru_size ru_size)166 hal_rx_ul_ofdma_ru_size_to_width(enum ath12k_eht_ru_size ru_size)
167 {
168 switch (ru_size) {
169 case ATH12K_EHT_RU_26:
170 return RU_26;
171 case ATH12K_EHT_RU_52:
172 return RU_52;
173 case ATH12K_EHT_RU_52_26:
174 return RU_52_26;
175 case ATH12K_EHT_RU_106:
176 return RU_106;
177 case ATH12K_EHT_RU_106_26:
178 return RU_106_26;
179 case ATH12K_EHT_RU_242:
180 return RU_242;
181 case ATH12K_EHT_RU_484:
182 return RU_484;
183 case ATH12K_EHT_RU_484_242:
184 return RU_484_242;
185 case ATH12K_EHT_RU_996:
186 return RU_996;
187 case ATH12K_EHT_RU_996_484:
188 return RU_996_484;
189 case ATH12K_EHT_RU_996_484_242:
190 return RU_996_484_242;
191 case ATH12K_EHT_RU_996x2:
192 return RU_2X996;
193 case ATH12K_EHT_RU_996x2_484:
194 return RU_2X996_484;
195 case ATH12K_EHT_RU_996x3:
196 return RU_3X996;
197 case ATH12K_EHT_RU_996x3_484:
198 return RU_3X996_484;
199 case ATH12K_EHT_RU_996x4:
200 return RU_4X996;
201 default:
202 return RU_INVALID;
203 }
204 }
205
206 static void
ath12k_wifi7_dp_mon_hal_rx_parse_user_info(const struct hal_receive_user_info * rx_usr_info,u16 user_id,struct hal_rx_mon_ppdu_info * ppdu_info)207 ath12k_wifi7_dp_mon_hal_rx_parse_user_info(const struct hal_receive_user_info *rx_usr_info,
208 u16 user_id,
209 struct hal_rx_mon_ppdu_info *ppdu_info)
210 {
211 struct hal_rx_user_status *mon_rx_user_status = NULL;
212 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
213 enum ath12k_eht_ru_size rtap_ru_size = ATH12K_EHT_RU_INVALID;
214 u32 ru_width, reception_type, ru_index = HAL_EHT_RU_INVALID;
215 u32 ru_type_80_0, ru_start_index_80_0;
216 u32 ru_type_80_1, ru_start_index_80_1;
217 u32 ru_type_80_2, ru_start_index_80_2;
218 u32 ru_type_80_3, ru_start_index_80_3;
219 u32 ru_size = 0, num_80mhz_with_ru = 0;
220 u64 ru_index_320mhz = 0;
221 u32 ru_index_per80mhz;
222
223 reception_type = le32_get_bits(rx_usr_info->info0,
224 HAL_RX_USR_INFO0_RECEPTION_TYPE);
225
226 switch (reception_type) {
227 case HAL_RECEPTION_TYPE_SU:
228 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
229 break;
230 case HAL_RECEPTION_TYPE_DL_MU_MIMO:
231 case HAL_RECEPTION_TYPE_UL_MU_MIMO:
232 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
233 break;
234 case HAL_RECEPTION_TYPE_DL_MU_OFMA:
235 case HAL_RECEPTION_TYPE_UL_MU_OFDMA:
236 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
237 break;
238 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO:
239 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO:
240 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO;
241 }
242
243 ppdu_info->is_stbc = le32_get_bits(rx_usr_info->info0, HAL_RX_USR_INFO0_STBC);
244 ppdu_info->ldpc = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_LDPC);
245 ppdu_info->dcm = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_STA_DCM);
246 ppdu_info->bw = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_RX_BW);
247 ppdu_info->mcs = le32_get_bits(rx_usr_info->info1, HAL_RX_USR_INFO1_MCS);
248 ppdu_info->nss = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_NSS) + 1;
249
250 if (user_id < HAL_MAX_UL_MU_USERS) {
251 mon_rx_user_status = &ppdu_info->userstats[user_id];
252 mon_rx_user_status->mcs = ppdu_info->mcs;
253 mon_rx_user_status->nss = ppdu_info->nss;
254 }
255
256 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO ||
257 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA ||
258 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO))
259 return;
260
261 /* RU allocation present only for OFDMA reception */
262 ru_type_80_0 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_0);
263 ru_start_index_80_0 = le32_get_bits(rx_usr_info->info3,
264 HAL_RX_USR_INFO3_RU_START_IDX_80_0);
265 if (ru_type_80_0 != HAL_EHT_RU_NONE) {
266 ru_size += ru_type_80_0;
267 ru_index_per80mhz = ru_start_index_80_0;
268 ru_index = ru_index_per80mhz;
269 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_0, 0, ru_index_per80mhz);
270 num_80mhz_with_ru++;
271 }
272
273 ru_type_80_1 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_1);
274 ru_start_index_80_1 = le32_get_bits(rx_usr_info->info3,
275 HAL_RX_USR_INFO3_RU_START_IDX_80_1);
276 if (ru_type_80_1 != HAL_EHT_RU_NONE) {
277 ru_size += ru_type_80_1;
278 ru_index_per80mhz = ru_start_index_80_1;
279 ru_index = ru_index_per80mhz;
280 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_1, 1, ru_index_per80mhz);
281 num_80mhz_with_ru++;
282 }
283
284 ru_type_80_2 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_2);
285 ru_start_index_80_2 = le32_get_bits(rx_usr_info->info3,
286 HAL_RX_USR_INFO3_RU_START_IDX_80_2);
287 if (ru_type_80_2 != HAL_EHT_RU_NONE) {
288 ru_size += ru_type_80_2;
289 ru_index_per80mhz = ru_start_index_80_2;
290 ru_index = ru_index_per80mhz;
291 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_2, 2, ru_index_per80mhz);
292 num_80mhz_with_ru++;
293 }
294
295 ru_type_80_3 = le32_get_bits(rx_usr_info->info2, HAL_RX_USR_INFO2_RU_TYPE_80_3);
296 ru_start_index_80_3 = le32_get_bits(rx_usr_info->info2,
297 HAL_RX_USR_INFO3_RU_START_IDX_80_3);
298 if (ru_type_80_3 != HAL_EHT_RU_NONE) {
299 ru_size += ru_type_80_3;
300 ru_index_per80mhz = ru_start_index_80_3;
301 ru_index = ru_index_per80mhz;
302 ru_index_320mhz |= HAL_RU_PER80(ru_type_80_3, 3, ru_index_per80mhz);
303 num_80mhz_with_ru++;
304 }
305
306 if (num_80mhz_with_ru > 1) {
307 /* Calculate the MRU index */
308 switch (ru_index_320mhz) {
309 case HAL_EHT_RU_996_484_0:
310 case HAL_EHT_RU_996x2_484_0:
311 case HAL_EHT_RU_996x3_484_0:
312 ru_index = 0;
313 break;
314 case HAL_EHT_RU_996_484_1:
315 case HAL_EHT_RU_996x2_484_1:
316 case HAL_EHT_RU_996x3_484_1:
317 ru_index = 1;
318 break;
319 case HAL_EHT_RU_996_484_2:
320 case HAL_EHT_RU_996x2_484_2:
321 case HAL_EHT_RU_996x3_484_2:
322 ru_index = 2;
323 break;
324 case HAL_EHT_RU_996_484_3:
325 case HAL_EHT_RU_996x2_484_3:
326 case HAL_EHT_RU_996x3_484_3:
327 ru_index = 3;
328 break;
329 case HAL_EHT_RU_996_484_4:
330 case HAL_EHT_RU_996x2_484_4:
331 case HAL_EHT_RU_996x3_484_4:
332 ru_index = 4;
333 break;
334 case HAL_EHT_RU_996_484_5:
335 case HAL_EHT_RU_996x2_484_5:
336 case HAL_EHT_RU_996x3_484_5:
337 ru_index = 5;
338 break;
339 case HAL_EHT_RU_996_484_6:
340 case HAL_EHT_RU_996x2_484_6:
341 case HAL_EHT_RU_996x3_484_6:
342 ru_index = 6;
343 break;
344 case HAL_EHT_RU_996_484_7:
345 case HAL_EHT_RU_996x2_484_7:
346 case HAL_EHT_RU_996x3_484_7:
347 ru_index = 7;
348 break;
349 case HAL_EHT_RU_996x2_484_8:
350 ru_index = 8;
351 break;
352 case HAL_EHT_RU_996x2_484_9:
353 ru_index = 9;
354 break;
355 case HAL_EHT_RU_996x2_484_10:
356 ru_index = 10;
357 break;
358 case HAL_EHT_RU_996x2_484_11:
359 ru_index = 11;
360 break;
361 default:
362 ru_index = HAL_EHT_RU_INVALID;
363 break;
364 }
365
366 ru_size += 4;
367 }
368
369 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ath12k_ru_size(ru_size);
370 if (rtap_ru_size != ATH12K_EHT_RU_INVALID) {
371 u32 known, data;
372
373 known = __le32_to_cpu(eht->known);
374 known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_SIZE_OM;
375 eht->known = cpu_to_le32(known);
376
377 data = __le32_to_cpu(eht->data[1]);
378 data |= u32_encode_bits(rtap_ru_size,
379 IEEE80211_RADIOTAP_EHT_DATA1_RU_SIZE);
380 eht->data[1] = cpu_to_le32(data);
381 }
382
383 if (ru_index != HAL_EHT_RU_INVALID) {
384 u32 known, data;
385
386 known = __le32_to_cpu(eht->known);
387 known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_INDEX_OM;
388 eht->known = cpu_to_le32(known);
389
390 data = __le32_to_cpu(eht->data[1]);
391 data |= u32_encode_bits(rtap_ru_size,
392 IEEE80211_RADIOTAP_EHT_DATA1_RU_INDEX);
393 eht->data[1] = cpu_to_le32(data);
394 }
395
396 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID &&
397 rtap_ru_size != ATH12K_EHT_RU_INVALID) {
398 mon_rx_user_status->ul_ofdma_ru_start_index = ru_index;
399 mon_rx_user_status->ul_ofdma_ru_size = rtap_ru_size;
400
401 ru_width = hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size);
402
403 mon_rx_user_status->ul_ofdma_ru_width = ru_width;
404 mon_rx_user_status->ofdma_info_valid = 1;
405 }
406 }
407
408 static void
ath12k_wifi7_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info * lsigb,struct hal_rx_mon_ppdu_info * ppdu_info)409 ath12k_wifi7_dp_mon_parse_l_sig_b(const struct hal_rx_lsig_b_info *lsigb,
410 struct hal_rx_mon_ppdu_info *ppdu_info)
411 {
412 u32 info0 = __le32_to_cpu(lsigb->info0);
413 u8 rate;
414
415 rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE);
416 switch (rate) {
417 case 1:
418 rate = HAL_RX_LEGACY_RATE_1_MBPS;
419 break;
420 case 2:
421 case 5:
422 rate = HAL_RX_LEGACY_RATE_2_MBPS;
423 break;
424 case 3:
425 case 6:
426 rate = HAL_RX_LEGACY_RATE_5_5_MBPS;
427 break;
428 case 4:
429 case 7:
430 rate = HAL_RX_LEGACY_RATE_11_MBPS;
431 break;
432 default:
433 rate = HAL_RX_LEGACY_RATE_INVALID;
434 }
435
436 ppdu_info->rate = rate;
437 ppdu_info->cck_flag = 1;
438 }
439
440 static void
ath12k_wifi7_dp_mon_parse_l_sig_a(const struct hal_rx_lsig_a_info * lsiga,struct hal_rx_mon_ppdu_info * ppdu_info)441 ath12k_wifi7_dp_mon_parse_l_sig_a(const struct hal_rx_lsig_a_info *lsiga,
442 struct hal_rx_mon_ppdu_info *ppdu_info)
443 {
444 u32 info0 = __le32_to_cpu(lsiga->info0);
445 u8 rate;
446
447 rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE);
448 switch (rate) {
449 case 8:
450 rate = HAL_RX_LEGACY_RATE_48_MBPS;
451 break;
452 case 9:
453 rate = HAL_RX_LEGACY_RATE_24_MBPS;
454 break;
455 case 10:
456 rate = HAL_RX_LEGACY_RATE_12_MBPS;
457 break;
458 case 11:
459 rate = HAL_RX_LEGACY_RATE_6_MBPS;
460 break;
461 case 12:
462 rate = HAL_RX_LEGACY_RATE_54_MBPS;
463 break;
464 case 13:
465 rate = HAL_RX_LEGACY_RATE_36_MBPS;
466 break;
467 case 14:
468 rate = HAL_RX_LEGACY_RATE_18_MBPS;
469 break;
470 case 15:
471 rate = HAL_RX_LEGACY_RATE_9_MBPS;
472 break;
473 default:
474 rate = HAL_RX_LEGACY_RATE_INVALID;
475 }
476
477 ppdu_info->rate = rate;
478 }
479
480 static void
ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn(const struct hal_mon_usig_cmn * cmn,struct hal_rx_mon_ppdu_info * ppdu_info)481 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn(const struct hal_mon_usig_cmn *cmn,
482 struct hal_rx_mon_ppdu_info *ppdu_info)
483 {
484 u32 common;
485
486 ppdu_info->u_sig_info.bw = le32_get_bits(cmn->info0,
487 HAL_RX_USIG_CMN_INFO0_BW);
488 ppdu_info->u_sig_info.ul_dl = le32_get_bits(cmn->info0,
489 HAL_RX_USIG_CMN_INFO0_UL_DL);
490
491 common = __le32_to_cpu(ppdu_info->u_sig_info.usig.common);
492 common |= IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER_KNOWN |
493 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN |
494 IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL_KNOWN |
495 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR_KNOWN |
496 IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP_KNOWN |
497 ATH12K_LE32_DEC_ENC(cmn->info0,
498 HAL_RX_USIG_CMN_INFO0_PHY_VERSION,
499 IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER) |
500 u32_encode_bits(ppdu_info->u_sig_info.bw,
501 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW) |
502 u32_encode_bits(ppdu_info->u_sig_info.ul_dl,
503 IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL) |
504 ATH12K_LE32_DEC_ENC(cmn->info0,
505 HAL_RX_USIG_CMN_INFO0_BSS_COLOR,
506 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR) |
507 ATH12K_LE32_DEC_ENC(cmn->info0,
508 HAL_RX_USIG_CMN_INFO0_TXOP,
509 IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP);
510 ppdu_info->u_sig_info.usig.common = cpu_to_le32(common);
511
512 switch (ppdu_info->u_sig_info.bw) {
513 default:
514 fallthrough;
515 case HAL_EHT_BW_20:
516 ppdu_info->bw = HAL_RX_BW_20MHZ;
517 break;
518 case HAL_EHT_BW_40:
519 ppdu_info->bw = HAL_RX_BW_40MHZ;
520 break;
521 case HAL_EHT_BW_80:
522 ppdu_info->bw = HAL_RX_BW_80MHZ;
523 break;
524 case HAL_EHT_BW_160:
525 ppdu_info->bw = HAL_RX_BW_160MHZ;
526 break;
527 case HAL_EHT_BW_320_1:
528 case HAL_EHT_BW_320_2:
529 ppdu_info->bw = HAL_RX_BW_320MHZ;
530 break;
531 }
532 }
533
534 static void
ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_tb(const struct hal_mon_usig_tb * usig_tb,struct hal_rx_mon_ppdu_info * ppdu_info)535 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_tb(const struct hal_mon_usig_tb *usig_tb,
536 struct hal_rx_mon_ppdu_info *ppdu_info)
537 {
538 struct ieee80211_radiotap_eht_usig *usig = &ppdu_info->u_sig_info.usig;
539 enum ieee80211_radiotap_eht_usig_tb spatial_reuse1, spatial_reuse2;
540 u32 common, value, mask;
541
542 spatial_reuse1 = IEEE80211_RADIOTAP_EHT_USIG2_TB_B3_B6_SPATIAL_REUSE_1;
543 spatial_reuse2 = IEEE80211_RADIOTAP_EHT_USIG2_TB_B7_B10_SPATIAL_REUSE_2;
544
545 common = __le32_to_cpu(usig->common);
546 value = __le32_to_cpu(usig->value);
547 mask = __le32_to_cpu(usig->mask);
548
549 ppdu_info->u_sig_info.ppdu_type_comp_mode =
550 le32_get_bits(usig_tb->info0,
551 HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE);
552
553 common |= ATH12K_LE32_DEC_ENC(usig_tb->info0,
554 HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS,
555 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BAD_USIG_CRC);
556
557 value |= IEEE80211_RADIOTAP_EHT_USIG1_TB_B20_B25_DISREGARD |
558 u32_encode_bits(ppdu_info->u_sig_info.ppdu_type_comp_mode,
559 IEEE80211_RADIOTAP_EHT_USIG2_TB_B0_B1_PPDU_TYPE) |
560 IEEE80211_RADIOTAP_EHT_USIG2_TB_B2_VALIDATE |
561 ATH12K_LE32_DEC_ENC(usig_tb->info0,
562 HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1,
563 spatial_reuse1) |
564 ATH12K_LE32_DEC_ENC(usig_tb->info0,
565 HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2,
566 spatial_reuse2) |
567 IEEE80211_RADIOTAP_EHT_USIG2_TB_B11_B15_DISREGARD |
568 ATH12K_LE32_DEC_ENC(usig_tb->info0,
569 HAL_RX_USIG_TB_INFO0_CRC,
570 IEEE80211_RADIOTAP_EHT_USIG2_TB_B16_B19_CRC) |
571 ATH12K_LE32_DEC_ENC(usig_tb->info0,
572 HAL_RX_USIG_TB_INFO0_TAIL,
573 IEEE80211_RADIOTAP_EHT_USIG2_TB_B20_B25_TAIL);
574
575 mask |= IEEE80211_RADIOTAP_EHT_USIG1_TB_B20_B25_DISREGARD |
576 IEEE80211_RADIOTAP_EHT_USIG2_TB_B0_B1_PPDU_TYPE |
577 IEEE80211_RADIOTAP_EHT_USIG2_TB_B2_VALIDATE |
578 spatial_reuse1 | spatial_reuse2 |
579 IEEE80211_RADIOTAP_EHT_USIG2_TB_B11_B15_DISREGARD |
580 IEEE80211_RADIOTAP_EHT_USIG2_TB_B16_B19_CRC |
581 IEEE80211_RADIOTAP_EHT_USIG2_TB_B20_B25_TAIL;
582
583 usig->common = cpu_to_le32(common);
584 usig->value = cpu_to_le32(value);
585 usig->mask = cpu_to_le32(mask);
586 }
587
588 static void
ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_mu(const struct hal_mon_usig_mu * usig_mu,struct hal_rx_mon_ppdu_info * ppdu_info)589 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_mu(const struct hal_mon_usig_mu *usig_mu,
590 struct hal_rx_mon_ppdu_info *ppdu_info)
591 {
592 struct ieee80211_radiotap_eht_usig *usig = &ppdu_info->u_sig_info.usig;
593 enum ieee80211_radiotap_eht_usig_mu sig_symb, punc;
594 u32 common, value, mask;
595
596 sig_symb = IEEE80211_RADIOTAP_EHT_USIG2_MU_B11_B15_EHT_SIG_SYMBOLS;
597 punc = IEEE80211_RADIOTAP_EHT_USIG2_MU_B3_B7_PUNCTURED_INFO;
598
599 common = __le32_to_cpu(usig->common);
600 value = __le32_to_cpu(usig->value);
601 mask = __le32_to_cpu(usig->mask);
602
603 ppdu_info->u_sig_info.ppdu_type_comp_mode =
604 le32_get_bits(usig_mu->info0,
605 HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE);
606 ppdu_info->u_sig_info.eht_sig_mcs =
607 le32_get_bits(usig_mu->info0,
608 HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS);
609 ppdu_info->u_sig_info.num_eht_sig_sym =
610 le32_get_bits(usig_mu->info0,
611 HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM);
612
613 common |= ATH12K_LE32_DEC_ENC(usig_mu->info0,
614 HAL_RX_USIG_MU_INFO0_RX_INTEG_CHECK_PASS,
615 IEEE80211_RADIOTAP_EHT_USIG_COMMON_BAD_USIG_CRC);
616
617 value |= IEEE80211_RADIOTAP_EHT_USIG1_MU_B20_B24_DISREGARD |
618 IEEE80211_RADIOTAP_EHT_USIG1_MU_B25_VALIDATE |
619 u32_encode_bits(ppdu_info->u_sig_info.ppdu_type_comp_mode,
620 IEEE80211_RADIOTAP_EHT_USIG2_MU_B0_B1_PPDU_TYPE) |
621 IEEE80211_RADIOTAP_EHT_USIG2_MU_B2_VALIDATE |
622 ATH12K_LE32_DEC_ENC(usig_mu->info0,
623 HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO,
624 punc) |
625 IEEE80211_RADIOTAP_EHT_USIG2_MU_B8_VALIDATE |
626 u32_encode_bits(ppdu_info->u_sig_info.eht_sig_mcs,
627 IEEE80211_RADIOTAP_EHT_USIG2_MU_B9_B10_SIG_MCS) |
628 u32_encode_bits(ppdu_info->u_sig_info.num_eht_sig_sym,
629 sig_symb) |
630 ATH12K_LE32_DEC_ENC(usig_mu->info0,
631 HAL_RX_USIG_MU_INFO0_CRC,
632 IEEE80211_RADIOTAP_EHT_USIG2_MU_B16_B19_CRC) |
633 ATH12K_LE32_DEC_ENC(usig_mu->info0,
634 HAL_RX_USIG_MU_INFO0_TAIL,
635 IEEE80211_RADIOTAP_EHT_USIG2_MU_B20_B25_TAIL);
636
637 mask |= IEEE80211_RADIOTAP_EHT_USIG1_MU_B20_B24_DISREGARD |
638 IEEE80211_RADIOTAP_EHT_USIG1_MU_B25_VALIDATE |
639 IEEE80211_RADIOTAP_EHT_USIG2_MU_B0_B1_PPDU_TYPE |
640 IEEE80211_RADIOTAP_EHT_USIG2_MU_B2_VALIDATE |
641 punc |
642 IEEE80211_RADIOTAP_EHT_USIG2_MU_B8_VALIDATE |
643 IEEE80211_RADIOTAP_EHT_USIG2_MU_B9_B10_SIG_MCS |
644 sig_symb |
645 IEEE80211_RADIOTAP_EHT_USIG2_MU_B16_B19_CRC |
646 IEEE80211_RADIOTAP_EHT_USIG2_MU_B20_B25_TAIL;
647
648 usig->common = cpu_to_le32(common);
649 usig->value = cpu_to_le32(value);
650 usig->mask = cpu_to_le32(mask);
651 }
652
653 static void
ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_hdr(const struct hal_mon_usig_hdr * usig,struct hal_rx_mon_ppdu_info * ppdu_info)654 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_hdr(const struct hal_mon_usig_hdr *usig,
655 struct hal_rx_mon_ppdu_info *ppdu_info)
656 {
657 u8 comp_mode;
658
659 ppdu_info->eht_usig = true;
660
661 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_cmn(&usig->cmn, ppdu_info);
662
663 comp_mode = le32_get_bits(usig->non_cmn.mu.info0,
664 HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE);
665
666 if (comp_mode == 0 && ppdu_info->u_sig_info.ul_dl)
667 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_tb(&usig->non_cmn.tb, ppdu_info);
668 else
669 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_mu(&usig->non_cmn.mu, ppdu_info);
670 }
671
672 static void
ath12k_wifi7_dp_mon_parse_vht_sig_a(const struct hal_rx_vht_sig_a_info * vht_sig,struct hal_rx_mon_ppdu_info * ppdu_info)673 ath12k_wifi7_dp_mon_parse_vht_sig_a(const struct hal_rx_vht_sig_a_info *vht_sig,
674 struct hal_rx_mon_ppdu_info *ppdu_info)
675 {
676 u32 nsts, info0, info1;
677 u8 gi_setting;
678
679 info0 = __le32_to_cpu(vht_sig->info0);
680 info1 = __le32_to_cpu(vht_sig->info1);
681
682 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
683 ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS);
684 gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING);
685 switch (gi_setting) {
686 case HAL_RX_VHT_SIG_A_NORMAL_GI:
687 ppdu_info->gi = HAL_RX_GI_0_8_US;
688 break;
689 case HAL_RX_VHT_SIG_A_SHORT_GI:
690 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
691 ppdu_info->gi = HAL_RX_GI_0_4_US;
692 break;
693 }
694
695 ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC);
696 nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS);
697 if (ppdu_info->is_stbc && nsts > 0)
698 nsts = ((nsts + 1) >> 1) - 1;
699
700 ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK) + 1;
701 ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW);
702 ppdu_info->beamformed = u32_get_bits(info1,
703 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED);
704 ppdu_info->vht_flag_values5 = u32_get_bits(info0,
705 HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID);
706 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) |
707 ppdu_info->nss);
708 ppdu_info->vht_flag_values2 = ppdu_info->bw;
709 ppdu_info->vht_flag_values4 =
710 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING);
711 }
712
713 static void
ath12k_wifi7_dp_mon_parse_ht_sig(const struct hal_rx_ht_sig_info * ht_sig,struct hal_rx_mon_ppdu_info * ppdu_info)714 ath12k_wifi7_dp_mon_parse_ht_sig(const struct hal_rx_ht_sig_info *ht_sig,
715 struct hal_rx_mon_ppdu_info *ppdu_info)
716 {
717 u32 info0 = __le32_to_cpu(ht_sig->info0);
718 u32 info1 = __le32_to_cpu(ht_sig->info1);
719
720 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS);
721 ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW);
722 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC);
723 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING);
724 ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI);
725 ppdu_info->nss = (ppdu_info->mcs >> 3) + 1;
726 }
727
728 static void
ath12k_wifi7_dp_mon_parse_he_sig_b2_ofdma(const struct hal_rx_he_sig_b2_ofdma_info * ofdma,struct hal_rx_mon_ppdu_info * ppdu_info)729 ath12k_wifi7_dp_mon_parse_he_sig_b2_ofdma(const struct hal_rx_he_sig_b2_ofdma_info *ofdma,
730 struct hal_rx_mon_ppdu_info *ppdu_info)
731 {
732 u32 info0, value;
733
734 info0 = __le32_to_cpu(ofdma->info0);
735
736 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN;
737
738 /* HE-data2 */
739 ppdu_info->he_data2 |= HE_TXBF_KNOWN;
740
741 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS);
742 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
743 ppdu_info->he_data3 |= value;
744
745 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM);
746 value = value << HE_DCM_SHIFT;
747 ppdu_info->he_data3 |= value;
748
749 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING);
750 ppdu_info->ldpc = value;
751 value = value << HE_CODING_SHIFT;
752 ppdu_info->he_data3 |= value;
753
754 /* HE-data4 */
755 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID);
756 value = value << HE_STA_ID_SHIFT;
757 ppdu_info->he_data4 |= value;
758
759 ppdu_info->nss =
760 u32_get_bits(info0,
761 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS) + 1;
762 ppdu_info->beamformed = u32_get_bits(info0,
763 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF);
764 }
765
766 static void
ath12k_wifi7_dp_mon_parse_he_sig_b2_mu(const struct hal_rx_he_sig_b2_mu_info * he_sig_b2_mu,struct hal_rx_mon_ppdu_info * ppdu_info)767 ath12k_wifi7_dp_mon_parse_he_sig_b2_mu(const struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu,
768 struct hal_rx_mon_ppdu_info *ppdu_info)
769 {
770 u32 info0, value;
771
772 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
773
774 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN;
775
776 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS);
777 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT;
778 ppdu_info->he_data3 |= value;
779
780 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING);
781 ppdu_info->ldpc = value;
782 value = value << HE_CODING_SHIFT;
783 ppdu_info->he_data3 |= value;
784
785 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID);
786 value = value << HE_STA_ID_SHIFT;
787 ppdu_info->he_data4 |= value;
788
789 ppdu_info->nss =
790 u32_get_bits(info0,
791 HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS) + 1;
792 }
793
794 static void
ath12k_wifi7_dp_mon_parse_he_sig_b1_mu(const struct hal_rx_he_sig_b1_mu_info * he_sig_b1_mu,struct hal_rx_mon_ppdu_info * ppdu_info)795 ath12k_wifi7_dp_mon_parse_he_sig_b1_mu(const struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu,
796 struct hal_rx_mon_ppdu_info *ppdu_info)
797 {
798 u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
799 u16 ru_tones;
800
801 ru_tones = u32_get_bits(info0,
802 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION);
803 ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
804 ppdu_info->he_RU[0] = ru_tones;
805 }
806
807 static void
ath12k_wifi7_dp_mon_parse_he_sig_mu(const struct hal_rx_he_sig_a_mu_dl_info * he_sig_a_mu_dl,struct hal_rx_mon_ppdu_info * ppdu_info)808 ath12k_wifi7_dp_mon_parse_he_sig_mu(const struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl,
809 struct hal_rx_mon_ppdu_info *ppdu_info)
810 {
811 u32 info0, info1, value;
812 u16 he_gi = 0, he_ltf = 0;
813
814 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
815 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
816
817 ppdu_info->he_mu_flags = 1;
818
819 ppdu_info->he_data1 = HE_MU_FORMAT_TYPE;
820 ppdu_info->he_data1 |=
821 HE_BSS_COLOR_KNOWN |
822 HE_DL_UL_KNOWN |
823 HE_LDPC_EXTRA_SYMBOL_KNOWN |
824 HE_STBC_KNOWN |
825 HE_DATA_BW_RU_KNOWN |
826 HE_DOPPLER_KNOWN;
827
828 ppdu_info->he_data2 =
829 HE_GI_KNOWN |
830 HE_LTF_SYMBOLS_KNOWN |
831 HE_PRE_FEC_PADDING_KNOWN |
832 HE_PE_DISAMBIGUITY_KNOWN |
833 HE_TXOP_KNOWN |
834 HE_MIDABLE_PERIODICITY_KNOWN;
835
836 /* data3 */
837 ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR);
838 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG);
839 value = value << HE_DL_UL_SHIFT;
840 ppdu_info->he_data3 |= value;
841
842 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA);
843 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
844 ppdu_info->he_data3 |= value;
845
846 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC);
847 value = value << HE_STBC_SHIFT;
848 ppdu_info->he_data3 |= value;
849
850 /* data4 */
851 ppdu_info->he_data4 = u32_get_bits(info0,
852 HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE);
853 ppdu_info->he_data4 = value;
854
855 /* data5 */
856 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
857 ppdu_info->he_data5 = value;
858 ppdu_info->bw = value;
859
860 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE);
861 switch (value) {
862 case 0:
863 he_gi = HE_GI_0_8;
864 he_ltf = HE_LTF_4_X;
865 break;
866 case 1:
867 he_gi = HE_GI_0_8;
868 he_ltf = HE_LTF_2_X;
869 break;
870 case 2:
871 he_gi = HE_GI_1_6;
872 he_ltf = HE_LTF_2_X;
873 break;
874 case 3:
875 he_gi = HE_GI_3_2;
876 he_ltf = HE_LTF_4_X;
877 break;
878 }
879
880 ppdu_info->gi = he_gi;
881 value = he_gi << HE_GI_SHIFT;
882 ppdu_info->he_data5 |= value;
883
884 value = he_ltf << HE_LTF_SIZE_SHIFT;
885 ppdu_info->he_data5 |= value;
886
887 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB);
888 value = (value << HE_LTF_SYM_SHIFT);
889 ppdu_info->he_data5 |= value;
890
891 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR);
892 value = value << HE_PRE_FEC_PAD_SHIFT;
893 ppdu_info->he_data5 |= value;
894
895 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM);
896 value = value << HE_PE_DISAMBIGUITY_SHIFT;
897 ppdu_info->he_data5 |= value;
898
899 /*data6*/
900 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION);
901 value = value << HE_DOPPLER_SHIFT;
902 ppdu_info->he_data6 |= value;
903
904 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION);
905 value = value << HE_TXOP_SHIFT;
906 ppdu_info->he_data6 |= value;
907
908 /* HE-MU Flags */
909 /* HE-MU-flags1 */
910 ppdu_info->he_flags1 =
911 HE_SIG_B_MCS_KNOWN |
912 HE_SIG_B_DCM_KNOWN |
913 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN |
914 HE_SIG_B_SYM_NUM_KNOWN |
915 HE_RU_0_KNOWN;
916
917 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB);
918 ppdu_info->he_flags1 |= value;
919 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB);
920 value = value << HE_DCM_FLAG_1_SHIFT;
921 ppdu_info->he_flags1 |= value;
922
923 /* HE-MU-flags2 */
924 ppdu_info->he_flags2 = HE_BW_KNOWN;
925
926 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW);
927 ppdu_info->he_flags2 |= value;
928 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB);
929 value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT;
930 ppdu_info->he_flags2 |= value;
931 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB);
932 value = value - 1;
933 value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT;
934 ppdu_info->he_flags2 |= value;
935
936 ppdu_info->is_stbc = info1 &
937 HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC;
938 }
939
940 static void
ath12k_wifi7_dp_mon_parse_he_sig_su(const struct hal_rx_he_sig_a_su_info * he_sig_a,struct hal_rx_mon_ppdu_info * ppdu_info)941 ath12k_wifi7_dp_mon_parse_he_sig_su(const struct hal_rx_he_sig_a_su_info *he_sig_a,
942 struct hal_rx_mon_ppdu_info *ppdu_info)
943 {
944 u32 info0, info1, value;
945 u32 dcm;
946 u8 he_dcm = 0, he_stbc = 0;
947 u16 he_gi = 0, he_ltf = 0;
948
949 ppdu_info->he_flags = 1;
950
951 info0 = __le32_to_cpu(he_sig_a->info0);
952 info1 = __le32_to_cpu(he_sig_a->info1);
953
954 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND);
955 if (value == 0)
956 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE;
957 else
958 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE;
959
960 ppdu_info->he_data1 |=
961 HE_BSS_COLOR_KNOWN |
962 HE_BEAM_CHANGE_KNOWN |
963 HE_DL_UL_KNOWN |
964 HE_MCS_KNOWN |
965 HE_DCM_KNOWN |
966 HE_CODING_KNOWN |
967 HE_LDPC_EXTRA_SYMBOL_KNOWN |
968 HE_STBC_KNOWN |
969 HE_DATA_BW_RU_KNOWN |
970 HE_DOPPLER_KNOWN;
971
972 ppdu_info->he_data2 |=
973 HE_GI_KNOWN |
974 HE_TXBF_KNOWN |
975 HE_PE_DISAMBIGUITY_KNOWN |
976 HE_TXOP_KNOWN |
977 HE_LTF_SYMBOLS_KNOWN |
978 HE_PRE_FEC_PADDING_KNOWN |
979 HE_MIDABLE_PERIODICITY_KNOWN;
980
981 ppdu_info->he_data3 = u32_get_bits(info0,
982 HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR);
983 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE);
984 value = value << HE_BEAM_CHANGE_SHIFT;
985 ppdu_info->he_data3 |= value;
986 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG);
987 value = value << HE_DL_UL_SHIFT;
988 ppdu_info->he_data3 |= value;
989
990 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
991 ppdu_info->mcs = value;
992 value = value << HE_TRANSMIT_MCS_SHIFT;
993 ppdu_info->he_data3 |= value;
994
995 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
996 he_dcm = value;
997 value = value << HE_DCM_SHIFT;
998 ppdu_info->he_data3 |= value;
999 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
1000 value = value << HE_CODING_SHIFT;
1001 ppdu_info->he_data3 |= value;
1002 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA);
1003 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT;
1004 ppdu_info->he_data3 |= value;
1005 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
1006 he_stbc = value;
1007 value = value << HE_STBC_SHIFT;
1008 ppdu_info->he_data3 |= value;
1009
1010 /* data4 */
1011 ppdu_info->he_data4 = u32_get_bits(info0,
1012 HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE);
1013
1014 /* data5 */
1015 value = u32_get_bits(info0,
1016 HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
1017 ppdu_info->he_data5 = value;
1018 ppdu_info->bw = value;
1019 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE);
1020 switch (value) {
1021 case 0:
1022 he_gi = HE_GI_0_8;
1023 he_ltf = HE_LTF_1_X;
1024 break;
1025 case 1:
1026 he_gi = HE_GI_0_8;
1027 he_ltf = HE_LTF_2_X;
1028 break;
1029 case 2:
1030 he_gi = HE_GI_1_6;
1031 he_ltf = HE_LTF_2_X;
1032 break;
1033 case 3:
1034 if (he_dcm && he_stbc) {
1035 he_gi = HE_GI_0_8;
1036 he_ltf = HE_LTF_4_X;
1037 } else {
1038 he_gi = HE_GI_3_2;
1039 he_ltf = HE_LTF_4_X;
1040 }
1041 break;
1042 }
1043 ppdu_info->gi = he_gi;
1044 value = he_gi << HE_GI_SHIFT;
1045 ppdu_info->he_data5 |= value;
1046 value = he_ltf << HE_LTF_SIZE_SHIFT;
1047 ppdu_info->ltf_size = he_ltf;
1048 ppdu_info->he_data5 |= value;
1049
1050 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
1051 value = (value << HE_LTF_SYM_SHIFT);
1052 ppdu_info->he_data5 |= value;
1053
1054 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR);
1055 value = value << HE_PRE_FEC_PAD_SHIFT;
1056 ppdu_info->he_data5 |= value;
1057
1058 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
1059 value = value << HE_TXBF_SHIFT;
1060 ppdu_info->he_data5 |= value;
1061 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM);
1062 value = value << HE_PE_DISAMBIGUITY_SHIFT;
1063 ppdu_info->he_data5 |= value;
1064
1065 /* data6 */
1066 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS);
1067 value++;
1068 ppdu_info->he_data6 = value;
1069 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND);
1070 value = value << HE_DOPPLER_SHIFT;
1071 ppdu_info->he_data6 |= value;
1072 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION);
1073 value = value << HE_TXOP_SHIFT;
1074 ppdu_info->he_data6 |= value;
1075
1076 ppdu_info->mcs =
1077 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS);
1078 ppdu_info->bw =
1079 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW);
1080 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING);
1081 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC);
1082 ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF);
1083 dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM);
1084 ppdu_info->nss = u32_get_bits(info0,
1085 HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS) + 1;
1086 ppdu_info->dcm = dcm;
1087 }
1088
1089 static inline bool
ath12k_wifi7_dp_mon_hal_rx_is_non_ofdma(const struct hal_rx_u_sig_info * usig_info)1090 ath12k_wifi7_dp_mon_hal_rx_is_non_ofdma(const struct hal_rx_u_sig_info *usig_info)
1091 {
1092 u32 ppdu_type_comp_mode = usig_info->ppdu_type_comp_mode;
1093 u32 ul_dl = usig_info->ul_dl;
1094
1095 if ((ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_MIMO && ul_dl == 0) ||
1096 (ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_OFDMA && ul_dl == 0) ||
1097 (ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_MIMO && ul_dl == 1))
1098 return true;
1099
1100 return false;
1101 }
1102
1103 static inline bool
ath12k_wifi7_dp_mon_hal_rx_is_ofdma(const struct hal_rx_u_sig_info * usig_info)1104 ath12k_wifi7_dp_mon_hal_rx_is_ofdma(const struct hal_rx_u_sig_info *usig_info)
1105 {
1106 if (usig_info->ppdu_type_comp_mode == 0 && usig_info->ul_dl == 0)
1107 return true;
1108
1109 return false;
1110 }
1111
1112 static inline bool
ath12k_wifi7_dp_mon_hal_rx_is_frame_type_ndp(const struct hal_rx_u_sig_info * usig_info)1113 ath12k_wifi7_dp_mon_hal_rx_is_frame_type_ndp(const struct hal_rx_u_sig_info *usig_info)
1114 {
1115 if (usig_info->ppdu_type_comp_mode == 1 &&
1116 usig_info->eht_sig_mcs == 0 &&
1117 usig_info->num_eht_sig_sym == 0)
1118 return true;
1119
1120 return false;
1121 }
1122
1123 static void
ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ndp(const struct hal_eht_sig_ndp_cmn_eb * eht_sig_ndp,struct hal_rx_mon_ppdu_info * ppdu_info)1124 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ndp(const struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp,
1125 struct hal_rx_mon_ppdu_info *ppdu_info)
1126 {
1127 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
1128 u32 known, data;
1129
1130 known = __le32_to_cpu(eht->known);
1131 known |= IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE |
1132 IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF |
1133 IEEE80211_RADIOTAP_EHT_KNOWN_NSS_S |
1134 IEEE80211_RADIOTAP_EHT_KNOWN_BEAMFORMED_S |
1135 IEEE80211_RADIOTAP_EHT_KNOWN_DISREGARD_S |
1136 IEEE80211_RADIOTAP_EHT_KNOWN_CRC1 |
1137 IEEE80211_RADIOTAP_EHT_KNOWN_TAIL1;
1138 eht->known = cpu_to_le32(known);
1139
1140 data = __le32_to_cpu(eht->data[0]);
1141 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
1142 HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE,
1143 IEEE80211_RADIOTAP_EHT_DATA0_SPATIAL_REUSE);
1144 /* GI and LTF size are separately indicated in radiotap header
1145 * and hence will be parsed from other TLV
1146 */
1147 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
1148 HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM,
1149 IEEE80211_RADIOTAP_EHT_DATA0_EHT_LTF);
1150
1151 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
1152 HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC,
1153 IEEE80211_RADIOTAP_EHT_DATA0_CRC1_O);
1154
1155 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
1156 HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD,
1157 IEEE80211_RADIOTAP_EHT_DATA0_DISREGARD_S);
1158 eht->data[0] = cpu_to_le32(data);
1159
1160 data = __le32_to_cpu(eht->data[7]);
1161 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
1162 HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS,
1163 IEEE80211_RADIOTAP_EHT_DATA7_NSS_S);
1164
1165 data |= ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0,
1166 HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED,
1167 IEEE80211_RADIOTAP_EHT_DATA7_BEAMFORMED_S);
1168 eht->data[7] = cpu_to_le32(data);
1169 }
1170
1171 static void
ath12k_wifi7_dp_mon_hal_rx_parse_usig_overflow(const struct hal_eht_sig_usig_overflow * ovflow,struct hal_rx_mon_ppdu_info * ppdu_info)1172 ath12k_wifi7_dp_mon_hal_rx_parse_usig_overflow(const struct hal_eht_sig_usig_overflow *ovflow,
1173 struct hal_rx_mon_ppdu_info *ppdu_info)
1174 {
1175 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
1176 u32 known, data;
1177
1178 known = __le32_to_cpu(eht->known);
1179 known |= IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE |
1180 IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF |
1181 IEEE80211_RADIOTAP_EHT_KNOWN_LDPC_EXTRA_SYM_OM |
1182 IEEE80211_RADIOTAP_EHT_KNOWN_PRE_PADD_FACOR_OM |
1183 IEEE80211_RADIOTAP_EHT_KNOWN_PE_DISAMBIGUITY_OM |
1184 IEEE80211_RADIOTAP_EHT_KNOWN_DISREGARD_O;
1185 eht->known = cpu_to_le32(known);
1186
1187 data = __le32_to_cpu(eht->data[0]);
1188 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
1189 HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE,
1190 IEEE80211_RADIOTAP_EHT_DATA0_SPATIAL_REUSE);
1191
1192 /* GI and LTF size are separately indicated in radiotap header
1193 * and hence will be parsed from other TLV
1194 */
1195 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
1196 HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM,
1197 IEEE80211_RADIOTAP_EHT_DATA0_EHT_LTF);
1198
1199 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
1200 HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM,
1201 IEEE80211_RADIOTAP_EHT_DATA0_LDPC_EXTRA_SYM_OM);
1202
1203 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
1204 HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR,
1205 IEEE80211_RADIOTAP_EHT_DATA0_PRE_PADD_FACOR_OM);
1206
1207 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
1208 HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY,
1209 IEEE80211_RADIOTAP_EHT_DATA0_PE_DISAMBIGUITY_OM);
1210
1211 data |= ATH12K_LE32_DEC_ENC(ovflow->info0,
1212 HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD,
1213 IEEE80211_RADIOTAP_EHT_DATA0_DISREGARD_O);
1214 eht->data[0] = cpu_to_le32(data);
1215 }
1216
1217 static void
ath12k_wifi7_dp_mon_hal_rx_parse_non_ofdma_users(const struct hal_eht_sig_non_ofdma_cmn_eb * eb,struct hal_rx_mon_ppdu_info * ppdu_info)1218 ath12k_wifi7_dp_mon_hal_rx_parse_non_ofdma_users(const struct hal_eht_sig_non_ofdma_cmn_eb *eb,
1219 struct hal_rx_mon_ppdu_info *ppdu_info)
1220 {
1221 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
1222 u32 known, data;
1223
1224 known = __le32_to_cpu(eht->known);
1225 known |= IEEE80211_RADIOTAP_EHT_KNOWN_NR_NON_OFDMA_USERS_M;
1226 eht->known = cpu_to_le32(known);
1227
1228 data = __le32_to_cpu(eht->data[7]);
1229 data |= ATH12K_LE32_DEC_ENC(eb->info0,
1230 HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS,
1231 IEEE80211_RADIOTAP_EHT_DATA7_NUM_OF_NON_OFDMA_USERS);
1232 eht->data[7] = cpu_to_le32(data);
1233 }
1234
1235 static void
ath12k_wifi7_dp_mon_hal_rx_parse_eht_mumimo_user(const struct hal_eht_sig_mu_mimo * user,struct hal_rx_mon_ppdu_info * ppdu_info)1236 ath12k_wifi7_dp_mon_hal_rx_parse_eht_mumimo_user(const struct hal_eht_sig_mu_mimo *user,
1237 struct hal_rx_mon_ppdu_info *ppdu_info)
1238 {
1239 struct hal_rx_eht_info *eht_info = &ppdu_info->eht_info;
1240 u32 user_idx;
1241
1242 if (eht_info->num_user_info >= ARRAY_SIZE(eht_info->user_info))
1243 return;
1244
1245 user_idx = eht_info->num_user_info++;
1246
1247 eht_info->user_info[user_idx] |=
1248 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID_KNOWN |
1249 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
1250 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN |
1251 IEEE80211_RADIOTAP_EHT_USER_INFO_SPATIAL_CONFIG_KNOWN_M |
1252 ATH12K_LE32_DEC_ENC(user->info0,
1253 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID,
1254 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID) |
1255 ATH12K_LE32_DEC_ENC(user->info0,
1256 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING,
1257 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING) |
1258 ATH12K_LE32_DEC_ENC(user->info0,
1259 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS,
1260 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
1261 ATH12K_LE32_DEC_ENC(user->info0,
1262 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING,
1263 IEEE80211_RADIOTAP_EHT_USER_INFO_SPATIAL_CONFIG_M);
1264
1265 ppdu_info->mcs = le32_get_bits(user->info0,
1266 HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS);
1267 }
1268
1269 static void
ath12k_wifi7_dp_mon_hal_rx_parse_eht_non_mumimo_user(const struct hal_eht_sig_non_mu_mimo * user,struct hal_rx_mon_ppdu_info * ppdu_info)1270 ath12k_wifi7_dp_mon_hal_rx_parse_eht_non_mumimo_user(const struct hal_eht_sig_non_mu_mimo *user,
1271 struct hal_rx_mon_ppdu_info *ppdu_info)
1272 {
1273 struct hal_rx_eht_info *eht_info = &ppdu_info->eht_info;
1274 u32 user_idx;
1275
1276 if (eht_info->num_user_info >= ARRAY_SIZE(eht_info->user_info))
1277 return;
1278
1279 user_idx = eht_info->num_user_info++;
1280
1281 eht_info->user_info[user_idx] |=
1282 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID_KNOWN |
1283 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
1284 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN |
1285 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
1286 IEEE80211_RADIOTAP_EHT_USER_INFO_BEAMFORMING_KNOWN_O |
1287 ATH12K_LE32_DEC_ENC(user->info0,
1288 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID,
1289 IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID) |
1290 ATH12K_LE32_DEC_ENC(user->info0,
1291 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING,
1292 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING) |
1293 ATH12K_LE32_DEC_ENC(user->info0,
1294 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS,
1295 IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
1296 ATH12K_LE32_DEC_ENC(user->info0,
1297 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS,
1298 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O) |
1299 ATH12K_LE32_DEC_ENC(user->info0,
1300 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED,
1301 IEEE80211_RADIOTAP_EHT_USER_INFO_BEAMFORMING_O);
1302
1303 ppdu_info->mcs = le32_get_bits(user->info0,
1304 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS);
1305
1306 ppdu_info->nss = le32_get_bits(user->info0,
1307 HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS) + 1;
1308 }
1309
1310 static inline bool
ath12k_wifi7_dp_mon_hal_rx_is_mu_mimo_user(const struct hal_rx_u_sig_info * usig_info)1311 ath12k_wifi7_dp_mon_hal_rx_is_mu_mimo_user(const struct hal_rx_u_sig_info *usig_info)
1312 {
1313 if (usig_info->ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_SU &&
1314 usig_info->ul_dl == 1)
1315 return true;
1316
1317 return false;
1318 }
1319
1320 static void
ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_non_ofdma(const void * tlv,struct hal_rx_mon_ppdu_info * ppdu_info)1321 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_non_ofdma(const void *tlv,
1322 struct hal_rx_mon_ppdu_info *ppdu_info)
1323 {
1324 const struct hal_eht_sig_non_ofdma_cmn_eb *eb = tlv;
1325
1326 ath12k_wifi7_dp_mon_hal_rx_parse_usig_overflow(tlv, ppdu_info);
1327 ath12k_wifi7_dp_mon_hal_rx_parse_non_ofdma_users(eb, ppdu_info);
1328
1329 if (ath12k_wifi7_dp_mon_hal_rx_is_mu_mimo_user(&ppdu_info->u_sig_info))
1330 ath12k_wifi7_dp_mon_hal_rx_parse_eht_mumimo_user(&eb->user_field.mu_mimo,
1331 ppdu_info);
1332 else
1333 ath12k_wifi7_dp_mon_hal_rx_parse_eht_non_mumimo_user(&eb->user_field.n_mu_mimo,
1334 ppdu_info);
1335 }
1336
1337 static void
ath12k_wifi7_dp_mon_hal_rx_parse_ru_allocation(const struct hal_eht_sig_ofdma_cmn_eb * eb,struct hal_rx_mon_ppdu_info * ppdu_info)1338 ath12k_wifi7_dp_mon_hal_rx_parse_ru_allocation(const struct hal_eht_sig_ofdma_cmn_eb *eb,
1339 struct hal_rx_mon_ppdu_info *ppdu_info)
1340 {
1341 const struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1 = &eb->eb1;
1342 const struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2 = &eb->eb2;
1343 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
1344 enum ieee80211_radiotap_eht_data ru_123, ru_124, ru_125, ru_126;
1345 enum ieee80211_radiotap_eht_data ru_121, ru_122, ru_112, ru_111;
1346 u32 data;
1347
1348 ru_123 = IEEE80211_RADIOTAP_EHT_DATA4_RU_ALLOC_CC_1_2_3;
1349 ru_124 = IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_4;
1350 ru_125 = IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_5;
1351 ru_126 = IEEE80211_RADIOTAP_EHT_DATA6_RU_ALLOC_CC_1_2_6;
1352 ru_121 = IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_1;
1353 ru_122 = IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_2;
1354 ru_112 = IEEE80211_RADIOTAP_EHT_DATA2_RU_ALLOC_CC_1_1_2;
1355 ru_111 = IEEE80211_RADIOTAP_EHT_DATA1_RU_ALLOC_CC_1_1_1;
1356
1357 switch (ppdu_info->u_sig_info.bw) {
1358 case HAL_EHT_BW_320_2:
1359 case HAL_EHT_BW_320_1:
1360 data = __le32_to_cpu(eht->data[4]);
1361 /* CC1 2::3 */
1362 data |= IEEE80211_RADIOTAP_EHT_DATA4_RU_ALLOC_CC_1_2_3_KNOWN |
1363 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1364 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3,
1365 ru_123);
1366 eht->data[4] = cpu_to_le32(data);
1367
1368 data = __le32_to_cpu(eht->data[5]);
1369 /* CC1 2::4 */
1370 data |= IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_4_KNOWN |
1371 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1372 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4,
1373 ru_124);
1374
1375 /* CC1 2::5 */
1376 data |= IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_5_KNOWN |
1377 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1378 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5,
1379 ru_125);
1380 eht->data[5] = cpu_to_le32(data);
1381
1382 data = __le32_to_cpu(eht->data[6]);
1383 /* CC1 2::6 */
1384 data |= IEEE80211_RADIOTAP_EHT_DATA6_RU_ALLOC_CC_1_2_6_KNOWN |
1385 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1386 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6,
1387 ru_126);
1388 eht->data[6] = cpu_to_le32(data);
1389
1390 fallthrough;
1391 case HAL_EHT_BW_160:
1392 data = __le32_to_cpu(eht->data[3]);
1393 /* CC1 2::1 */
1394 data |= IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_1_KNOWN |
1395 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1396 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1,
1397 ru_121);
1398 /* CC1 2::2 */
1399 data |= IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_2_KNOWN |
1400 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0,
1401 HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2,
1402 ru_122);
1403 eht->data[3] = cpu_to_le32(data);
1404
1405 fallthrough;
1406 case HAL_EHT_BW_80:
1407 data = __le32_to_cpu(eht->data[2]);
1408 /* CC1 1::2 */
1409 data |= IEEE80211_RADIOTAP_EHT_DATA2_RU_ALLOC_CC_1_1_2_KNOWN |
1410 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb1->info0,
1411 HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2,
1412 ru_112);
1413 eht->data[2] = cpu_to_le32(data);
1414
1415 fallthrough;
1416 case HAL_EHT_BW_40:
1417 fallthrough;
1418 case HAL_EHT_BW_20:
1419 data = __le32_to_cpu(eht->data[1]);
1420 /* CC1 1::1 */
1421 data |= IEEE80211_RADIOTAP_EHT_DATA1_RU_ALLOC_CC_1_1_1_KNOWN |
1422 ATH12K_LE64_DEC_ENC(ofdma_cmn_eb1->info0,
1423 HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1,
1424 ru_111);
1425 eht->data[1] = cpu_to_le32(data);
1426 break;
1427 default:
1428 break;
1429 }
1430 }
1431
1432 static void
ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ofdma(const void * tlv,struct hal_rx_mon_ppdu_info * ppdu_info)1433 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ofdma(const void *tlv,
1434 struct hal_rx_mon_ppdu_info *ppdu_info)
1435 {
1436 const struct hal_eht_sig_ofdma_cmn_eb *ofdma = tlv;
1437
1438 ath12k_wifi7_dp_mon_hal_rx_parse_usig_overflow(tlv, ppdu_info);
1439 ath12k_wifi7_dp_mon_hal_rx_parse_ru_allocation(ofdma, ppdu_info);
1440
1441 ath12k_wifi7_dp_mon_hal_rx_parse_eht_non_mumimo_user(&ofdma->user_field.n_mu_mimo,
1442 ppdu_info);
1443 }
1444
1445 static void
ath12k_wifi7_dp_mon_parse_eht_sig_hdr(struct hal_rx_mon_ppdu_info * ppdu_info,const void * tlv_data)1446 ath12k_wifi7_dp_mon_parse_eht_sig_hdr(struct hal_rx_mon_ppdu_info *ppdu_info,
1447 const void *tlv_data)
1448 {
1449 ppdu_info->is_eht = true;
1450
1451 if (ath12k_wifi7_dp_mon_hal_rx_is_frame_type_ndp(&ppdu_info->u_sig_info))
1452 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ndp(tlv_data, ppdu_info);
1453 else if (ath12k_wifi7_dp_mon_hal_rx_is_non_ofdma(&ppdu_info->u_sig_info))
1454 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_non_ofdma(tlv_data, ppdu_info);
1455 else if (ath12k_wifi7_dp_mon_hal_rx_is_ofdma(&ppdu_info->u_sig_info))
1456 ath12k_wifi7_dp_mon_hal_rx_parse_eht_sig_ofdma(tlv_data, ppdu_info);
1457 }
1458
ath12k_wifi7_dp_mon_parse_rx_msdu_end_err(u32 info,u32 * errmap)1459 static void ath12k_wifi7_dp_mon_parse_rx_msdu_end_err(u32 info, u32 *errmap)
1460 {
1461 if (info & RX_MSDU_END_INFO13_FCS_ERR)
1462 *errmap |= HAL_RX_MPDU_ERR_FCS;
1463
1464 if (info & RX_MSDU_END_INFO13_DECRYPT_ERR)
1465 *errmap |= HAL_RX_MPDU_ERR_DECRYPT;
1466
1467 if (info & RX_MSDU_END_INFO13_TKIP_MIC_ERR)
1468 *errmap |= HAL_RX_MPDU_ERR_TKIP_MIC;
1469
1470 if (info & RX_MSDU_END_INFO13_A_MSDU_ERROR)
1471 *errmap |= HAL_RX_MPDU_ERR_AMSDU_ERR;
1472
1473 if (info & RX_MSDU_END_INFO13_OVERFLOW_ERR)
1474 *errmap |= HAL_RX_MPDU_ERR_OVERFLOW;
1475
1476 if (info & RX_MSDU_END_INFO13_MSDU_LEN_ERR)
1477 *errmap |= HAL_RX_MPDU_ERR_MSDU_LEN;
1478
1479 if (info & RX_MSDU_END_INFO13_MPDU_LEN_ERR)
1480 *errmap |= HAL_RX_MPDU_ERR_MPDU_LEN;
1481 }
1482
1483 static void
ath12k_wifi7_parse_cmn_usr_info(const struct hal_phyrx_common_user_info * cmn_usr_info,struct hal_rx_mon_ppdu_info * ppdu_info)1484 ath12k_wifi7_parse_cmn_usr_info(const struct hal_phyrx_common_user_info *cmn_usr_info,
1485 struct hal_rx_mon_ppdu_info *ppdu_info)
1486 {
1487 struct hal_rx_radiotap_eht *eht = &ppdu_info->eht_info.eht;
1488 u32 known, data, cp_setting, ltf_size;
1489
1490 known = __le32_to_cpu(eht->known);
1491 known |= IEEE80211_RADIOTAP_EHT_KNOWN_GI |
1492 IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF;
1493 eht->known = cpu_to_le32(known);
1494
1495 cp_setting = le32_get_bits(cmn_usr_info->info0,
1496 HAL_RX_CMN_USR_INFO0_CP_SETTING);
1497 ltf_size = le32_get_bits(cmn_usr_info->info0,
1498 HAL_RX_CMN_USR_INFO0_LTF_SIZE);
1499
1500 data = __le32_to_cpu(eht->data[0]);
1501 data |= u32_encode_bits(cp_setting, IEEE80211_RADIOTAP_EHT_DATA0_GI);
1502 data |= u32_encode_bits(ltf_size, IEEE80211_RADIOTAP_EHT_DATA0_LTF);
1503 eht->data[0] = cpu_to_le32(data);
1504
1505 if (!ppdu_info->ltf_size)
1506 ppdu_info->ltf_size = ltf_size;
1507 if (!ppdu_info->gi)
1508 ppdu_info->gi = cp_setting;
1509 }
1510
1511 static void
ath12k_wifi7_dp_mon_parse_status_msdu_end(struct ath12k_mon_data * pmon,const struct hal_rx_msdu_end * msdu_end)1512 ath12k_wifi7_dp_mon_parse_status_msdu_end(struct ath12k_mon_data *pmon,
1513 const struct hal_rx_msdu_end *msdu_end)
1514 {
1515 ath12k_wifi7_dp_mon_parse_rx_msdu_end_err(__le32_to_cpu(msdu_end->info2),
1516 &pmon->err_bitmap);
1517 pmon->decap_format = le32_get_bits(msdu_end->info1,
1518 RX_MSDU_END_INFO11_DECAP_FORMAT);
1519 }
1520
1521 static enum hal_rx_mon_status
ath12k_wifi7_dp_mon_rx_parse_status_tlv(struct ath12k_pdev_dp * dp_pdev,struct ath12k_mon_data * pmon,const struct hal_tlv_64_hdr * tlv)1522 ath12k_wifi7_dp_mon_rx_parse_status_tlv(struct ath12k_pdev_dp *dp_pdev,
1523 struct ath12k_mon_data *pmon,
1524 const struct hal_tlv_64_hdr *tlv)
1525 {
1526 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
1527 const void *tlv_data = tlv->value;
1528 u32 info[7], userid;
1529 u16 tlv_tag, tlv_len;
1530
1531 tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG);
1532 tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN);
1533 userid = le64_get_bits(tlv->tl, HAL_TLV_64_USR_ID);
1534
1535 if (ppdu_info->tlv_aggr.in_progress && ppdu_info->tlv_aggr.tlv_tag != tlv_tag) {
1536 ath12k_wifi7_dp_mon_parse_eht_sig_hdr(ppdu_info,
1537 ppdu_info->tlv_aggr.buf);
1538
1539 ppdu_info->tlv_aggr.in_progress = false;
1540 ppdu_info->tlv_aggr.cur_len = 0;
1541 }
1542
1543 switch (tlv_tag) {
1544 case HAL_RX_PPDU_START: {
1545 const struct hal_rx_ppdu_start *ppdu_start = tlv_data;
1546
1547 u64 ppdu_ts = ath12k_le32hilo_to_u64(ppdu_start->ppdu_start_ts_63_32,
1548 ppdu_start->ppdu_start_ts_31_0);
1549
1550 info[0] = __le32_to_cpu(ppdu_start->info0);
1551
1552 ppdu_info->ppdu_id = u32_get_bits(info[0],
1553 HAL_RX_PPDU_START_INFO0_PPDU_ID);
1554
1555 info[1] = __le32_to_cpu(ppdu_start->info1);
1556 ppdu_info->chan_num = u32_get_bits(info[1],
1557 HAL_RX_PPDU_START_INFO1_CHAN_NUM);
1558 ppdu_info->freq = u32_get_bits(info[1],
1559 HAL_RX_PPDU_START_INFO1_CHAN_FREQ);
1560 ppdu_info->ppdu_ts = ppdu_ts;
1561
1562 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) {
1563 ppdu_info->last_ppdu_id = ppdu_info->ppdu_id;
1564 ppdu_info->num_users = 0;
1565 memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0,
1566 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
1567 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0]));
1568 }
1569 break;
1570 }
1571 case HAL_RX_PPDU_END_USER_STATS: {
1572 const struct hal_rx_ppdu_end_user_stats *eu_stats = tlv_data;
1573 u32 tid_bitmap;
1574
1575 info[0] = __le32_to_cpu(eu_stats->info0);
1576 info[1] = __le32_to_cpu(eu_stats->info1);
1577 info[2] = __le32_to_cpu(eu_stats->info2);
1578 info[4] = __le32_to_cpu(eu_stats->info4);
1579 info[5] = __le32_to_cpu(eu_stats->info5);
1580 info[6] = __le32_to_cpu(eu_stats->info6);
1581
1582 ppdu_info->ast_index =
1583 u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX);
1584 ppdu_info->fc_valid =
1585 u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID);
1586 tid_bitmap = u32_get_bits(info[6],
1587 HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP);
1588 ppdu_info->tid = ffs(tid_bitmap) - 1;
1589 ppdu_info->tcp_msdu_count =
1590 u32_get_bits(info[4],
1591 HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT);
1592 ppdu_info->udp_msdu_count =
1593 u32_get_bits(info[4],
1594 HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT);
1595 ppdu_info->other_msdu_count =
1596 u32_get_bits(info[5],
1597 HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT);
1598 ppdu_info->tcp_ack_msdu_count =
1599 u32_get_bits(info[5],
1600 HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT);
1601 ppdu_info->preamble_type =
1602 u32_get_bits(info[1],
1603 HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE);
1604 ppdu_info->num_mpdu_fcs_ok =
1605 u32_get_bits(info[1],
1606 HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK);
1607 ppdu_info->num_mpdu_fcs_err =
1608 u32_get_bits(info[0],
1609 HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR);
1610 ppdu_info->peer_id =
1611 u32_get_bits(info[0], HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID);
1612
1613 switch (ppdu_info->preamble_type) {
1614 case HAL_RX_PREAMBLE_11N:
1615 ppdu_info->ht_flags = 1;
1616 break;
1617 case HAL_RX_PREAMBLE_11AC:
1618 ppdu_info->vht_flags = 1;
1619 break;
1620 case HAL_RX_PREAMBLE_11AX:
1621 ppdu_info->he_flags = 1;
1622 break;
1623 case HAL_RX_PREAMBLE_11BE:
1624 ppdu_info->is_eht = true;
1625 break;
1626 default:
1627 break;
1628 }
1629
1630 if (userid < HAL_MAX_UL_MU_USERS) {
1631 struct hal_rx_user_status *rxuser_stats =
1632 &ppdu_info->userstats[userid];
1633
1634 if (ppdu_info->num_mpdu_fcs_ok > 1 ||
1635 ppdu_info->num_mpdu_fcs_err > 1)
1636 ppdu_info->userstats[userid].ampdu_present = true;
1637
1638 ppdu_info->num_users += 1;
1639
1640 ath12k_wifi7_dp_mon_rx_handle_ofdma_info(eu_stats, rxuser_stats);
1641 ath12k_wifi7_dp_mon_rx_populate_mu_user_info(eu_stats, ppdu_info,
1642 rxuser_stats);
1643 }
1644 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]);
1645 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]);
1646 break;
1647 }
1648 case HAL_RX_PPDU_END_USER_STATS_EXT: {
1649 const struct hal_rx_ppdu_end_user_stats_ext *eu_stats = tlv_data;
1650
1651 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1);
1652 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2);
1653 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3);
1654 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4);
1655 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5);
1656 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6);
1657 break;
1658 }
1659 case HAL_PHYRX_HT_SIG:
1660 ath12k_wifi7_dp_mon_parse_ht_sig(tlv_data, ppdu_info);
1661 break;
1662
1663 case HAL_PHYRX_L_SIG_B:
1664 ath12k_wifi7_dp_mon_parse_l_sig_b(tlv_data, ppdu_info);
1665 break;
1666
1667 case HAL_PHYRX_L_SIG_A:
1668 ath12k_wifi7_dp_mon_parse_l_sig_a(tlv_data, ppdu_info);
1669 break;
1670
1671 case HAL_PHYRX_VHT_SIG_A:
1672 ath12k_wifi7_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info);
1673 break;
1674
1675 case HAL_PHYRX_HE_SIG_A_SU:
1676 ath12k_wifi7_dp_mon_parse_he_sig_su(tlv_data, ppdu_info);
1677 break;
1678
1679 case HAL_PHYRX_HE_SIG_A_MU_DL:
1680 ath12k_wifi7_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info);
1681 break;
1682
1683 case HAL_PHYRX_HE_SIG_B1_MU:
1684 ath12k_wifi7_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info);
1685 break;
1686
1687 case HAL_PHYRX_HE_SIG_B2_MU:
1688 ath12k_wifi7_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info);
1689 break;
1690
1691 case HAL_PHYRX_HE_SIG_B2_OFDMA:
1692 ath12k_wifi7_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info);
1693 break;
1694
1695 case HAL_PHYRX_RSSI_LEGACY: {
1696 const struct hal_rx_phyrx_rssi_legacy_info *rssi = tlv_data;
1697
1698 info[0] = __le32_to_cpu(rssi->info0);
1699 info[2] = __le32_to_cpu(rssi->info2);
1700
1701 /* TODO: Please note that the combined rssi will not be accurate
1702 * in MU case. Rssi in MU needs to be retrieved from
1703 * PHYRX_OTHER_RECEIVE_INFO TLV.
1704 */
1705 ppdu_info->rssi_comb =
1706 u32_get_bits(info[2],
1707 HAL_RX_RSSI_LEGACY_INFO_INFO2_RSSI_COMB_PPDU);
1708
1709 ppdu_info->bw = u32_get_bits(info[0],
1710 HAL_RX_RSSI_LEGACY_INFO_INFO0_RX_BW);
1711 break;
1712 }
1713 case HAL_PHYRX_COMMON_USER_INFO: {
1714 ath12k_wifi7_parse_cmn_usr_info(tlv_data, ppdu_info);
1715 break;
1716 }
1717 case HAL_RX_PPDU_START_USER_INFO:
1718 ath12k_wifi7_dp_mon_hal_rx_parse_user_info(tlv_data, userid, ppdu_info);
1719 break;
1720
1721 case HAL_RXPCU_PPDU_END_INFO: {
1722 const struct hal_rx_ppdu_end_duration *ppdu_rx_duration = tlv_data;
1723
1724 info[0] = __le32_to_cpu(ppdu_rx_duration->info0);
1725 ppdu_info->rx_duration =
1726 u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION);
1727 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]);
1728 ppdu_info->tsft = (ppdu_info->tsft << 32) |
1729 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]);
1730 break;
1731 }
1732 case HAL_RX_MPDU_START: {
1733 const struct hal_rx_mpdu_start *mpdu_start = tlv_data;
1734 u16 peer_id;
1735
1736 info[1] = __le32_to_cpu(mpdu_start->info1);
1737 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID);
1738 if (peer_id)
1739 ppdu_info->peer_id = peer_id;
1740
1741 ppdu_info->mpdu_len += u32_get_bits(info[1],
1742 HAL_RX_MPDU_START_INFO2_MPDU_LEN);
1743 if (userid < HAL_MAX_UL_MU_USERS) {
1744 info[0] = __le32_to_cpu(mpdu_start->info0);
1745 ppdu_info->userid = userid;
1746 ppdu_info->userstats[userid].ampdu_id =
1747 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO0_PPDU_ID);
1748 }
1749
1750 return HAL_RX_MON_STATUS_MPDU_START;
1751 }
1752 case HAL_RX_MSDU_START:
1753 /* TODO: add msdu start parsing logic */
1754 break;
1755 case HAL_MON_BUF_ADDR:
1756 return HAL_RX_MON_STATUS_BUF_ADDR;
1757 case HAL_RX_MSDU_END:
1758 ath12k_wifi7_dp_mon_parse_status_msdu_end(pmon, tlv_data);
1759 return HAL_RX_MON_STATUS_MSDU_END;
1760 case HAL_RX_MPDU_END:
1761 return HAL_RX_MON_STATUS_MPDU_END;
1762 case HAL_PHYRX_GENERIC_U_SIG:
1763 ath12k_wifi7_dp_mon_hal_rx_parse_u_sig_hdr(tlv_data, ppdu_info);
1764 break;
1765 case HAL_PHYRX_GENERIC_EHT_SIG:
1766 /* Handle the case where aggregation is in progress
1767 * or the current TLV is one of the TLVs which should be
1768 * aggregated
1769 */
1770 if (!ppdu_info->tlv_aggr.in_progress) {
1771 ppdu_info->tlv_aggr.in_progress = true;
1772 ppdu_info->tlv_aggr.tlv_tag = tlv_tag;
1773 ppdu_info->tlv_aggr.cur_len = 0;
1774 }
1775
1776 ppdu_info->is_eht = true;
1777
1778 ath12k_wifi7_dp_mon_hal_aggr_tlv(ppdu_info, tlv_len, tlv_data);
1779 break;
1780 case HAL_DUMMY:
1781 return HAL_RX_MON_STATUS_BUF_DONE;
1782 case HAL_RX_PPDU_END_STATUS_DONE:
1783 case 0:
1784 return HAL_RX_MON_STATUS_PPDU_DONE;
1785 default:
1786 break;
1787 }
1788
1789 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
1790 }
1791
1792 static int
ath12k_wifi7_dp_mon_parse_rx_dest_tlv(struct ath12k_pdev_dp * dp_pdev,struct ath12k_mon_data * pmon,enum hal_rx_mon_status hal_status,const void * tlv_data)1793 ath12k_wifi7_dp_mon_parse_rx_dest_tlv(struct ath12k_pdev_dp *dp_pdev,
1794 struct ath12k_mon_data *pmon,
1795 enum hal_rx_mon_status hal_status,
1796 const void *tlv_data)
1797 {
1798 switch (hal_status) {
1799 case HAL_RX_MON_STATUS_MPDU_START:
1800 if (WARN_ON_ONCE(pmon->mon_mpdu))
1801 break;
1802
1803 pmon->mon_mpdu = kzalloc_obj(*pmon->mon_mpdu, GFP_ATOMIC);
1804 if (!pmon->mon_mpdu)
1805 return -ENOMEM;
1806 break;
1807 case HAL_RX_MON_STATUS_BUF_ADDR:
1808 return ath12k_dp_mon_parse_status_buf(dp_pdev, pmon, tlv_data);
1809 case HAL_RX_MON_STATUS_MPDU_END:
1810 /* If no MSDU then free empty MPDU */
1811 if (pmon->mon_mpdu->tail) {
1812 pmon->mon_mpdu->tail->next = NULL;
1813 list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list);
1814 } else {
1815 kfree(pmon->mon_mpdu);
1816 }
1817 pmon->mon_mpdu = NULL;
1818 break;
1819 case HAL_RX_MON_STATUS_MSDU_END:
1820 pmon->mon_mpdu->decap_format = pmon->decap_format;
1821 pmon->mon_mpdu->err_bitmap = pmon->err_bitmap;
1822 break;
1823 default:
1824 break;
1825 }
1826
1827 return 0;
1828 }
1829
1830 static struct dp_mon_tx_ppdu_info *
ath12k_wifi7_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data * pmon,unsigned int ppdu_id,enum dp_mon_tx_ppdu_info_type type)1831 ath12k_wifi7_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon,
1832 unsigned int ppdu_id,
1833 enum dp_mon_tx_ppdu_info_type type)
1834 {
1835 struct dp_mon_tx_ppdu_info *tx_ppdu_info;
1836
1837 if (type == DP_MON_TX_PROT_PPDU_INFO) {
1838 tx_ppdu_info = pmon->tx_prot_ppdu_info;
1839
1840 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1841 return tx_ppdu_info;
1842 kfree(tx_ppdu_info);
1843 } else {
1844 tx_ppdu_info = pmon->tx_data_ppdu_info;
1845
1846 if (tx_ppdu_info && !tx_ppdu_info->is_used)
1847 return tx_ppdu_info;
1848 kfree(tx_ppdu_info);
1849 }
1850
1851 /* allocate new tx_ppdu_info */
1852 tx_ppdu_info = kzalloc_obj(*tx_ppdu_info, GFP_ATOMIC);
1853 if (!tx_ppdu_info)
1854 return NULL;
1855
1856 tx_ppdu_info->is_used = 0;
1857 tx_ppdu_info->ppdu_id = ppdu_id;
1858
1859 if (type == DP_MON_TX_PROT_PPDU_INFO)
1860 pmon->tx_prot_ppdu_info = tx_ppdu_info;
1861 else
1862 pmon->tx_data_ppdu_info = tx_ppdu_info;
1863
1864 return tx_ppdu_info;
1865 }
1866
1867 static struct dp_mon_tx_ppdu_info *
ath12k_wifi7_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data * pmon,u16 tlv_tag)1868 ath12k_wifi7_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon,
1869 u16 tlv_tag)
1870 {
1871 switch (tlv_tag) {
1872 case HAL_TX_FES_SETUP:
1873 case HAL_TX_FLUSH:
1874 case HAL_PCU_PPDU_SETUP_INIT:
1875 case HAL_TX_PEER_ENTRY:
1876 case HAL_TX_QUEUE_EXTENSION:
1877 case HAL_TX_MPDU_START:
1878 case HAL_TX_MSDU_START:
1879 case HAL_TX_DATA:
1880 case HAL_MON_BUF_ADDR:
1881 case HAL_TX_MPDU_END:
1882 case HAL_TX_LAST_MPDU_FETCHED:
1883 case HAL_TX_LAST_MPDU_END:
1884 case HAL_COEX_TX_REQ:
1885 case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP:
1886 case HAL_SCH_CRITICAL_TLV_REFERENCE:
1887 case HAL_TX_FES_SETUP_COMPLETE:
1888 case HAL_TQM_MPDU_GLOBAL_START:
1889 case HAL_SCHEDULER_END:
1890 case HAL_TX_FES_STATUS_USER_PPDU:
1891 break;
1892 case HAL_TX_FES_STATUS_PROT: {
1893 if (!pmon->tx_prot_ppdu_info->is_used)
1894 pmon->tx_prot_ppdu_info->is_used = true;
1895
1896 return pmon->tx_prot_ppdu_info;
1897 }
1898 }
1899
1900 if (!pmon->tx_data_ppdu_info->is_used)
1901 pmon->tx_data_ppdu_info->is_used = true;
1902
1903 return pmon->tx_data_ppdu_info;
1904 }
1905
1906 #define MAX_MONITOR_HEADER 512
1907 #define MAX_DUMMY_FRM_BODY 128
1908
1909 static struct
ath12k_wifi7_dp_mon_tx_alloc_skb(void)1910 sk_buff *ath12k_wifi7_dp_mon_tx_alloc_skb(void)
1911 {
1912 struct sk_buff *skb;
1913
1914 skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY);
1915 if (!skb)
1916 return NULL;
1917
1918 skb_reserve(skb, MAX_MONITOR_HEADER);
1919
1920 if (!IS_ALIGNED((unsigned long)skb->data, 4))
1921 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data);
1922
1923 return skb;
1924 }
1925
1926 static int
ath12k_wifi7_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1927 ath12k_wifi7_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1928 {
1929 struct sk_buff *skb;
1930 struct ieee80211_cts *cts;
1931
1932 skb = ath12k_wifi7_dp_mon_tx_alloc_skb();
1933 if (!skb)
1934 return -ENOMEM;
1935
1936 cts = (struct ieee80211_cts *)skb->data;
1937 memset(cts, 0, MAX_DUMMY_FRM_BODY);
1938 cts->frame_control =
1939 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS);
1940 cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1941 memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra));
1942
1943 skb_put(skb, sizeof(*cts));
1944 tx_ppdu_info->tx_mon_mpdu->head = skb;
1945 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1946 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1947 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1948
1949 return 0;
1950 }
1951
1952 static int
ath12k_wifi7_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1953 ath12k_wifi7_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1954 {
1955 struct sk_buff *skb;
1956 struct ieee80211_rts *rts;
1957
1958 skb = ath12k_wifi7_dp_mon_tx_alloc_skb();
1959 if (!skb)
1960 return -ENOMEM;
1961
1962 rts = (struct ieee80211_rts *)skb->data;
1963 memset(rts, 0, MAX_DUMMY_FRM_BODY);
1964 rts->frame_control =
1965 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS);
1966 rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1967 memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra));
1968 memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta));
1969
1970 skb_put(skb, sizeof(*rts));
1971 tx_ppdu_info->tx_mon_mpdu->head = skb;
1972 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
1973 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
1974 &tx_ppdu_info->dp_tx_mon_mpdu_list);
1975
1976 return 0;
1977 }
1978
1979 static int
ath12k_wifi7_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)1980 ath12k_wifi7_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
1981 {
1982 struct sk_buff *skb;
1983 struct ieee80211_qos_hdr *qhdr;
1984
1985 skb = ath12k_wifi7_dp_mon_tx_alloc_skb();
1986 if (!skb)
1987 return -ENOMEM;
1988
1989 qhdr = (struct ieee80211_qos_hdr *)skb->data;
1990 memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
1991 qhdr->frame_control =
1992 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
1993 qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
1994 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
1995 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
1996 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
1997
1998 skb_put(skb, sizeof(*qhdr));
1999 tx_ppdu_info->tx_mon_mpdu->head = skb;
2000 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
2001 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2002 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2003
2004 return 0;
2005 }
2006
2007 static int
ath12k_wifi7_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2008 ath12k_wifi7_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2009 {
2010 struct sk_buff *skb;
2011 struct dp_mon_qosframe_addr4 *qhdr;
2012
2013 skb = ath12k_wifi7_dp_mon_tx_alloc_skb();
2014 if (!skb)
2015 return -ENOMEM;
2016
2017 qhdr = (struct dp_mon_qosframe_addr4 *)skb->data;
2018 memset(qhdr, 0, MAX_DUMMY_FRM_BODY);
2019 qhdr->frame_control =
2020 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC);
2021 qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration);
2022 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
2023 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN);
2024 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN);
2025 memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN);
2026
2027 skb_put(skb, sizeof(*qhdr));
2028 tx_ppdu_info->tx_mon_mpdu->head = skb;
2029 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
2030 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2031 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2032
2033 return 0;
2034 }
2035
2036 static int
ath12k_wifi7_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2037 ath12k_wifi7_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2038 {
2039 struct sk_buff *skb;
2040 struct dp_mon_frame_min_one *fbmhdr;
2041
2042 skb = ath12k_wifi7_dp_mon_tx_alloc_skb();
2043 if (!skb)
2044 return -ENOMEM;
2045
2046 fbmhdr = (struct dp_mon_frame_min_one *)skb->data;
2047 memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY);
2048 fbmhdr->frame_control =
2049 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK);
2050 memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN);
2051
2052 /* set duration zero for ack frame */
2053 fbmhdr->duration = 0;
2054
2055 skb_put(skb, sizeof(*fbmhdr));
2056 tx_ppdu_info->tx_mon_mpdu->head = skb;
2057 tx_ppdu_info->tx_mon_mpdu->tail = NULL;
2058 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2059 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2060
2061 return 0;
2062 }
2063
2064 static int
ath12k_wifi7_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info * tx_ppdu_info)2065 ath12k_wifi7_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2066 {
2067 int ret = 0;
2068
2069 switch (tx_ppdu_info->rx_status.medium_prot_type) {
2070 case DP_MON_TX_MEDIUM_RTS_LEGACY:
2071 case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW:
2072 case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW:
2073 ret = ath12k_wifi7_dp_mon_tx_gen_rts_frame(tx_ppdu_info);
2074 break;
2075 case DP_MON_TX_MEDIUM_CTS2SELF:
2076 ret = ath12k_wifi7_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
2077 break;
2078 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR:
2079 ret = ath12k_wifi7_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info);
2080 break;
2081 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR:
2082 ret = ath12k_wifi7_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info);
2083 break;
2084 }
2085
2086 return ret;
2087 }
2088
2089 static enum dp_mon_tx_tlv_status
ath12k_wifi7_dp_mon_tx_parse_status_tlv(struct ath12k_base * ab,struct ath12k_mon_data * pmon,u16 tlv_tag,const void * tlv_data,u32 userid)2090 ath12k_wifi7_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab,
2091 struct ath12k_mon_data *pmon,
2092 u16 tlv_tag, const void *tlv_data,
2093 u32 userid)
2094 {
2095 struct dp_mon_tx_ppdu_info *tx_ppdu_info;
2096 enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
2097 u32 info[7];
2098
2099 tx_ppdu_info = ath12k_wifi7_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag);
2100
2101 switch (tlv_tag) {
2102 case HAL_TX_FES_SETUP: {
2103 const struct hal_tx_fes_setup *tx_fes_setup = tlv_data;
2104
2105 info[0] = __le32_to_cpu(tx_fes_setup->info0);
2106 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id);
2107 tx_ppdu_info->num_users =
2108 u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
2109 status = DP_MON_TX_FES_SETUP;
2110 break;
2111 }
2112
2113 case HAL_TX_FES_STATUS_END: {
2114 const struct hal_tx_fes_status_end *tx_fes_status_end = tlv_data;
2115 u32 tst_15_0, tst_31_16;
2116
2117 info[0] = __le32_to_cpu(tx_fes_status_end->info0);
2118 tst_15_0 =
2119 u32_get_bits(info[0],
2120 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0);
2121 tst_31_16 =
2122 u32_get_bits(info[0],
2123 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16);
2124
2125 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16));
2126 status = DP_MON_TX_FES_STATUS_END;
2127 break;
2128 }
2129
2130 case HAL_RX_RESPONSE_REQUIRED_INFO: {
2131 const struct hal_rx_resp_req_info *rx_resp_req_info = tlv_data;
2132 u32 addr_32;
2133 u16 addr_16;
2134
2135 info[0] = __le32_to_cpu(rx_resp_req_info->info0);
2136 info[1] = __le32_to_cpu(rx_resp_req_info->info1);
2137 info[2] = __le32_to_cpu(rx_resp_req_info->info2);
2138 info[3] = __le32_to_cpu(rx_resp_req_info->info3);
2139 info[4] = __le32_to_cpu(rx_resp_req_info->info4);
2140 info[5] = __le32_to_cpu(rx_resp_req_info->info5);
2141
2142 tx_ppdu_info->rx_status.ppdu_id =
2143 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID);
2144 tx_ppdu_info->rx_status.reception_type =
2145 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE);
2146 tx_ppdu_info->rx_status.rx_duration =
2147 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION);
2148 tx_ppdu_info->rx_status.mcs =
2149 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS);
2150 tx_ppdu_info->rx_status.sgi =
2151 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI);
2152 tx_ppdu_info->rx_status.is_stbc =
2153 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC);
2154 tx_ppdu_info->rx_status.ldpc =
2155 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC);
2156 tx_ppdu_info->rx_status.is_ampdu =
2157 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU);
2158 tx_ppdu_info->rx_status.num_users =
2159 u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER);
2160
2161 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0);
2162 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32);
2163 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
2164
2165 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0);
2166 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16);
2167 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
2168
2169 if (tx_ppdu_info->rx_status.reception_type == 0)
2170 ath12k_wifi7_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info);
2171 status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
2172 break;
2173 }
2174
2175 case HAL_PCU_PPDU_SETUP_INIT: {
2176 const struct hal_tx_pcu_ppdu_setup_init *ppdu_setup = tlv_data;
2177 u32 addr_32;
2178 u16 addr_16;
2179
2180 info[0] = __le32_to_cpu(ppdu_setup->info0);
2181 info[1] = __le32_to_cpu(ppdu_setup->info1);
2182 info[2] = __le32_to_cpu(ppdu_setup->info2);
2183 info[3] = __le32_to_cpu(ppdu_setup->info3);
2184 info[4] = __le32_to_cpu(ppdu_setup->info4);
2185 info[5] = __le32_to_cpu(ppdu_setup->info5);
2186 info[6] = __le32_to_cpu(ppdu_setup->info6);
2187
2188 /* protection frame address 1 */
2189 addr_32 = u32_get_bits(info[1],
2190 HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0);
2191 addr_16 = u32_get_bits(info[2],
2192 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32);
2193 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
2194
2195 /* protection frame address 2 */
2196 addr_16 = u32_get_bits(info[2],
2197 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0);
2198 addr_32 = u32_get_bits(info[3],
2199 HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16);
2200 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2);
2201
2202 /* protection frame address 3 */
2203 addr_32 = u32_get_bits(info[4],
2204 HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0);
2205 addr_16 = u32_get_bits(info[5],
2206 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32);
2207 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3);
2208
2209 /* protection frame address 4 */
2210 addr_16 = u32_get_bits(info[5],
2211 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0);
2212 addr_32 = u32_get_bits(info[6],
2213 HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16);
2214 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4);
2215
2216 status = u32_get_bits(info[0],
2217 HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE);
2218 break;
2219 }
2220
2221 case HAL_TX_QUEUE_EXTENSION: {
2222 const struct hal_tx_queue_exten *tx_q_exten = tlv_data;
2223
2224 info[0] = __le32_to_cpu(tx_q_exten->info0);
2225
2226 tx_ppdu_info->rx_status.frame_control =
2227 u32_get_bits(info[0],
2228 HAL_TX_Q_EXT_INFO0_FRAME_CTRL);
2229 tx_ppdu_info->rx_status.fc_valid = true;
2230 break;
2231 }
2232
2233 case HAL_TX_FES_STATUS_START: {
2234 const struct hal_tx_fes_status_start *tx_fes_start = tlv_data;
2235
2236 info[0] = __le32_to_cpu(tx_fes_start->info0);
2237
2238 tx_ppdu_info->rx_status.medium_prot_type =
2239 u32_get_bits(info[0],
2240 HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE);
2241 break;
2242 }
2243
2244 case HAL_TX_FES_STATUS_PROT: {
2245 const struct hal_tx_fes_status_prot *tx_fes_status = tlv_data;
2246 u32 start_timestamp;
2247 u32 end_timestamp;
2248
2249 info[0] = __le32_to_cpu(tx_fes_status->info0);
2250 info[1] = __le32_to_cpu(tx_fes_status->info1);
2251
2252 start_timestamp =
2253 u32_get_bits(info[0],
2254 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0);
2255 start_timestamp |=
2256 u32_get_bits(info[0],
2257 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15;
2258 end_timestamp =
2259 u32_get_bits(info[1],
2260 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0);
2261 end_timestamp |=
2262 u32_get_bits(info[1],
2263 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15;
2264 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp;
2265
2266 ath12k_wifi7_dp_mon_tx_gen_prot_frame(tx_ppdu_info);
2267 break;
2268 }
2269
2270 case HAL_TX_FES_STATUS_START_PPDU:
2271 case HAL_TX_FES_STATUS_START_PROT: {
2272 const struct hal_tx_fes_status_start_prot *tx_fes_stat_start = tlv_data;
2273 u64 ppdu_ts;
2274
2275 info[0] = __le32_to_cpu(tx_fes_stat_start->info0);
2276
2277 tx_ppdu_info->rx_status.ppdu_ts =
2278 u32_get_bits(info[0],
2279 HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32);
2280 ppdu_ts = (u32_get_bits(info[1],
2281 HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32));
2282 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32;
2283 break;
2284 }
2285
2286 case HAL_TX_FES_STATUS_USER_PPDU: {
2287 const struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu = tlv_data;
2288
2289 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0);
2290
2291 tx_ppdu_info->rx_status.rx_duration =
2292 u32_get_bits(info[0],
2293 HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION);
2294 break;
2295 }
2296
2297 case HAL_MACTX_HE_SIG_A_SU:
2298 ath12k_wifi7_dp_mon_parse_he_sig_su(tlv_data,
2299 &tx_ppdu_info->rx_status);
2300 break;
2301
2302 case HAL_MACTX_HE_SIG_A_MU_DL:
2303 ath12k_wifi7_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status);
2304 break;
2305
2306 case HAL_MACTX_HE_SIG_B1_MU:
2307 ath12k_wifi7_dp_mon_parse_he_sig_b1_mu(tlv_data,
2308 &tx_ppdu_info->rx_status);
2309 break;
2310
2311 case HAL_MACTX_HE_SIG_B2_MU:
2312 ath12k_wifi7_dp_mon_parse_he_sig_b2_mu(tlv_data,
2313 &tx_ppdu_info->rx_status);
2314 break;
2315
2316 case HAL_MACTX_HE_SIG_B2_OFDMA:
2317 ath12k_wifi7_dp_mon_parse_he_sig_b2_ofdma(tlv_data,
2318 &tx_ppdu_info->rx_status);
2319 break;
2320
2321 case HAL_MACTX_VHT_SIG_A:
2322 ath12k_wifi7_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status);
2323 break;
2324
2325 case HAL_MACTX_L_SIG_A:
2326 ath12k_wifi7_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status);
2327 break;
2328
2329 case HAL_MACTX_L_SIG_B:
2330 ath12k_wifi7_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status);
2331 break;
2332
2333 case HAL_RX_FRAME_BITMAP_ACK: {
2334 const struct hal_rx_frame_bitmap_ack *fbm_ack = tlv_data;
2335 u32 addr_32;
2336 u16 addr_16;
2337
2338 info[0] = __le32_to_cpu(fbm_ack->info0);
2339 info[1] = __le32_to_cpu(fbm_ack->info1);
2340
2341 addr_32 = u32_get_bits(info[0],
2342 HAL_RX_FBM_ACK_INFO0_ADDR1_31_0);
2343 addr_16 = u32_get_bits(info[1],
2344 HAL_RX_FBM_ACK_INFO1_ADDR1_47_32);
2345 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1);
2346
2347 ath12k_wifi7_dp_mon_tx_gen_ack_frame(tx_ppdu_info);
2348 break;
2349 }
2350
2351 case HAL_MACTX_PHY_DESC: {
2352 const struct hal_tx_phy_desc *tx_phy_desc = tlv_data;
2353
2354 info[0] = __le32_to_cpu(tx_phy_desc->info0);
2355 info[1] = __le32_to_cpu(tx_phy_desc->info1);
2356 info[2] = __le32_to_cpu(tx_phy_desc->info2);
2357 info[3] = __le32_to_cpu(tx_phy_desc->info3);
2358
2359 tx_ppdu_info->rx_status.beamformed =
2360 u32_get_bits(info[0],
2361 HAL_TX_PHY_DESC_INFO0_BF_TYPE);
2362 tx_ppdu_info->rx_status.preamble_type =
2363 u32_get_bits(info[0],
2364 HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B);
2365 tx_ppdu_info->rx_status.mcs =
2366 u32_get_bits(info[1],
2367 HAL_TX_PHY_DESC_INFO1_MCS);
2368 tx_ppdu_info->rx_status.ltf_size =
2369 u32_get_bits(info[3],
2370 HAL_TX_PHY_DESC_INFO3_LTF_SIZE);
2371 tx_ppdu_info->rx_status.nss =
2372 u32_get_bits(info[2],
2373 HAL_TX_PHY_DESC_INFO2_NSS);
2374 tx_ppdu_info->rx_status.chan_num =
2375 u32_get_bits(info[3],
2376 HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL);
2377 tx_ppdu_info->rx_status.bw =
2378 u32_get_bits(info[0],
2379 HAL_TX_PHY_DESC_INFO0_BANDWIDTH);
2380 break;
2381 }
2382
2383 case HAL_TX_MPDU_START: {
2384 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu;
2385
2386 mon_mpdu = kzalloc_obj(*mon_mpdu, GFP_ATOMIC);
2387 if (!mon_mpdu)
2388 return DP_MON_TX_STATUS_PPDU_NOT_DONE;
2389 status = DP_MON_TX_MPDU_START;
2390 break;
2391 }
2392
2393 case HAL_TX_MPDU_END:
2394 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list,
2395 &tx_ppdu_info->dp_tx_mon_mpdu_list);
2396 break;
2397 }
2398
2399 return status;
2400 }
2401
2402 static enum dp_mon_tx_tlv_status
ath12k_wifi7_dp_mon_tx_status_get_num_user(u16 tlv_tag,struct hal_tlv_hdr * tx_tlv,u8 * num_users)2403 ath12k_wifi7_dp_mon_tx_status_get_num_user(u16 tlv_tag,
2404 struct hal_tlv_hdr *tx_tlv,
2405 u8 *num_users)
2406 {
2407 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
2408 u32 info0;
2409
2410 switch (tlv_tag) {
2411 case HAL_TX_FES_SETUP: {
2412 struct hal_tx_fes_setup *tx_fes_setup =
2413 (struct hal_tx_fes_setup *)tx_tlv;
2414
2415 info0 = __le32_to_cpu(tx_fes_setup->info0);
2416
2417 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS);
2418 tlv_status = DP_MON_TX_FES_SETUP;
2419 break;
2420 }
2421
2422 case HAL_RX_RESPONSE_REQUIRED_INFO: {
2423 /* TODO: need to update *num_users */
2424 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO;
2425 break;
2426 }
2427 }
2428
2429 return tlv_status;
2430 }
2431
2432 static int
ath12k_wifi7_dp_mon_rx_deliver(struct ath12k_pdev_dp * dp_pdev,struct dp_mon_mpdu * mon_mpdu,struct hal_rx_mon_ppdu_info * ppduinfo,struct napi_struct * napi)2433 ath12k_wifi7_dp_mon_rx_deliver(struct ath12k_pdev_dp *dp_pdev,
2434 struct dp_mon_mpdu *mon_mpdu,
2435 struct hal_rx_mon_ppdu_info *ppduinfo,
2436 struct napi_struct *napi)
2437 {
2438 struct sk_buff *mon_skb, *skb_next, *header;
2439 struct ieee80211_rx_status *rxs = &dp_pdev->rx_status;
2440 u8 decap = DP_RX_DECAP_TYPE_RAW;
2441
2442 mon_skb = ath12k_dp_mon_rx_merg_msdus(dp_pdev, mon_mpdu, ppduinfo, rxs);
2443 if (!mon_skb)
2444 goto mon_deliver_fail;
2445
2446 header = mon_skb;
2447 rxs->flag = 0;
2448
2449 if (mon_mpdu->err_bitmap & HAL_RX_MPDU_ERR_FCS)
2450 rxs->flag = RX_FLAG_FAILED_FCS_CRC;
2451
2452 do {
2453 skb_next = mon_skb->next;
2454 if (!skb_next)
2455 rxs->flag &= ~RX_FLAG_AMSDU_MORE;
2456 else
2457 rxs->flag |= RX_FLAG_AMSDU_MORE;
2458
2459 if (mon_skb == header) {
2460 header = NULL;
2461 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
2462 } else {
2463 rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
2464 }
2465 rxs->flag |= RX_FLAG_ONLY_MONITOR;
2466
2467 if (!(rxs->flag & RX_FLAG_ONLY_MONITOR))
2468 decap = mon_mpdu->decap_format;
2469
2470 ath12k_dp_mon_update_radiotap(dp_pdev, ppduinfo, mon_skb, rxs);
2471 ath12k_dp_mon_rx_deliver_msdu(dp_pdev, napi, mon_skb, ppduinfo,
2472 rxs, decap);
2473 mon_skb = skb_next;
2474 } while (mon_skb);
2475 rxs->flag = 0;
2476
2477 return 0;
2478
2479 mon_deliver_fail:
2480 mon_skb = mon_mpdu->head;
2481 while (mon_skb) {
2482 skb_next = mon_skb->next;
2483 dev_kfree_skb_any(mon_skb);
2484 mon_skb = skb_next;
2485 }
2486 return -EINVAL;
2487 }
2488
2489 static void
ath12k_wifi7_dp_mon_tx_process_ppdu_info(struct ath12k_pdev_dp * dp_pdev,struct napi_struct * napi,struct dp_mon_tx_ppdu_info * tx_ppdu_info)2490 ath12k_wifi7_dp_mon_tx_process_ppdu_info(struct ath12k_pdev_dp *dp_pdev,
2491 struct napi_struct *napi,
2492 struct dp_mon_tx_ppdu_info *tx_ppdu_info)
2493 {
2494 struct dp_mon_mpdu *tmp, *mon_mpdu;
2495
2496 list_for_each_entry_safe(mon_mpdu, tmp,
2497 &tx_ppdu_info->dp_tx_mon_mpdu_list, list) {
2498 list_del(&mon_mpdu->list);
2499
2500 if (mon_mpdu->head)
2501 ath12k_wifi7_dp_mon_rx_deliver(dp_pdev, mon_mpdu,
2502 &tx_ppdu_info->rx_status, napi);
2503
2504 kfree(mon_mpdu);
2505 }
2506 }
2507
2508 enum hal_rx_mon_status
ath12k_wifi7_dp_mon_tx_parse_mon_status(struct ath12k_pdev_dp * dp_pdev,struct ath12k_mon_data * pmon,struct sk_buff * skb,struct napi_struct * napi,u32 ppdu_id)2509 ath12k_wifi7_dp_mon_tx_parse_mon_status(struct ath12k_pdev_dp *dp_pdev,
2510 struct ath12k_mon_data *pmon,
2511 struct sk_buff *skb,
2512 struct napi_struct *napi,
2513 u32 ppdu_id)
2514 {
2515 struct ath12k_dp *dp = dp_pdev->dp;
2516 struct ath12k_base *ab = dp->ab;
2517 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info;
2518 struct hal_tlv_hdr *tlv;
2519 u8 *ptr = skb->data;
2520 u16 tlv_tag;
2521 u16 tlv_len;
2522 u32 tlv_userid = 0;
2523 u8 num_user;
2524 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE;
2525
2526 tx_prot_ppdu_info =
2527 ath12k_wifi7_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
2528 DP_MON_TX_PROT_PPDU_INFO);
2529 if (!tx_prot_ppdu_info)
2530 return -ENOMEM;
2531
2532 tlv = (struct hal_tlv_hdr *)ptr;
2533 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
2534
2535 tlv_status = ath12k_wifi7_dp_mon_tx_status_get_num_user(tlv_tag, tlv,
2536 &num_user);
2537 if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user)
2538 return -EINVAL;
2539
2540 tx_data_ppdu_info =
2541 ath12k_wifi7_dp_mon_tx_get_ppdu_info(pmon, ppdu_id,
2542 DP_MON_TX_DATA_PPDU_INFO);
2543 if (!tx_data_ppdu_info)
2544 return -ENOMEM;
2545
2546 do {
2547 tlv = (struct hal_tlv_hdr *)ptr;
2548 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG);
2549 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN);
2550 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID);
2551
2552 tlv_status = ath12k_wifi7_dp_mon_tx_parse_status_tlv(ab, pmon,
2553 tlv_tag, ptr,
2554 tlv_userid);
2555 ptr += tlv_len;
2556 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
2557 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE)
2558 break;
2559 } while (tlv_status != DP_MON_TX_FES_STATUS_END);
2560
2561 ath12k_wifi7_dp_mon_tx_process_ppdu_info(dp_pdev, napi, tx_data_ppdu_info);
2562 ath12k_wifi7_dp_mon_tx_process_ppdu_info(dp_pdev, napi, tx_prot_ppdu_info);
2563
2564 return tlv_status;
2565 }
2566
2567 static void
ath12k_wifi7_dp_mon_next_link_desc_get(struct ath12k_base * ab,struct hal_rx_msdu_link * msdu_link,dma_addr_t * paddr,u32 * sw_cookie,u8 * rbm,struct ath12k_buffer_addr ** pp_buf_addr_info)2568 ath12k_wifi7_dp_mon_next_link_desc_get(struct ath12k_base *ab,
2569 struct hal_rx_msdu_link *msdu_link,
2570 dma_addr_t *paddr, u32 *sw_cookie, u8 *rbm,
2571 struct ath12k_buffer_addr **pp_buf_addr_info)
2572 {
2573 struct ath12k_buffer_addr *buf_addr_info;
2574
2575 buf_addr_info = &msdu_link->buf_addr_info;
2576
2577 ath12k_wifi7_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
2578
2579 *pp_buf_addr_info = buf_addr_info;
2580 }
2581
2582 static u32
ath12k_wifi7_dp_rx_mon_mpdu_pop(struct ath12k * ar,int mac_id,void * ring_entry,struct sk_buff ** head_msdu,struct sk_buff ** tail_msdu,struct list_head * used_list,u32 * npackets,u32 * ppdu_id)2583 ath12k_wifi7_dp_rx_mon_mpdu_pop(struct ath12k *ar, int mac_id,
2584 void *ring_entry, struct sk_buff **head_msdu,
2585 struct sk_buff **tail_msdu,
2586 struct list_head *used_list,
2587 u32 *npackets, u32 *ppdu_id)
2588 {
2589 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&ar->dp.mon_data;
2590 struct ath12k_base *ab = ar->ab;
2591 struct ath12k_dp *dp = ath12k_ab_to_dp(ab);
2592 struct ath12k_buffer_addr *p_buf_addr_info, *p_last_buf_addr_info;
2593 u32 msdu_ppdu_id = 0, msdu_cnt = 0, total_len = 0, frag_len = 0;
2594 u32 rx_buf_size, rx_pkt_offset, sw_cookie;
2595 bool is_frag, is_first_msdu, drop_mpdu = false;
2596 struct hal_reo_entrance_ring *ent_desc =
2597 (struct hal_reo_entrance_ring *)ring_entry;
2598 u32 rx_bufs_used = 0, i = 0, desc_bank = 0;
2599 struct hal_rx_desc *rx_desc, *tail_rx_desc;
2600 struct hal_rx_msdu_link *msdu_link_desc;
2601 struct sk_buff *msdu = NULL, *last = NULL;
2602 struct ath12k_rx_desc_info *desc_info;
2603 struct ath12k_buffer_addr buf_info;
2604 struct hal_rx_msdu_list msdu_list;
2605 struct ath12k_skb_rxcb *rxcb;
2606 u16 num_msdus = 0;
2607 dma_addr_t paddr;
2608 u8 rbm;
2609
2610 ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
2611 &sw_cookie,
2612 &p_last_buf_addr_info,
2613 &rbm,
2614 &msdu_cnt);
2615
2616 spin_lock_bh(&pmon->mon_lock);
2617
2618 if (le32_get_bits(ent_desc->info1,
2619 HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON) ==
2620 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
2621 u8 rxdma_err = le32_get_bits(ent_desc->info1,
2622 HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE);
2623 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
2624 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
2625 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
2626 drop_mpdu = true;
2627 pmon->rx_mon_stats.dest_mpdu_drop++;
2628 }
2629 }
2630
2631 is_frag = false;
2632 is_first_msdu = true;
2633 rx_pkt_offset = sizeof(struct hal_rx_desc);
2634
2635 do {
2636 if (pmon->mon_last_linkdesc_paddr == paddr) {
2637 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
2638 spin_unlock_bh(&pmon->mon_lock);
2639 return rx_bufs_used;
2640 }
2641
2642 desc_bank = u32_get_bits(sw_cookie, DP_LINK_DESC_BANK_MASK);
2643 msdu_link_desc =
2644 dp->link_desc_banks[desc_bank].vaddr +
2645 (paddr - dp->link_desc_banks[desc_bank].paddr);
2646
2647 ath12k_wifi7_hal_rx_msdu_list_get(ar, msdu_link_desc, &msdu_list,
2648 &num_msdus);
2649 desc_info = ath12k_dp_get_rx_desc(ar->ab->dp,
2650 msdu_list.sw_cookie[num_msdus - 1]);
2651 tail_rx_desc = (struct hal_rx_desc *)(desc_info->skb)->data;
2652
2653 for (i = 0; i < num_msdus; i++) {
2654 u32 l2_hdr_offset;
2655
2656 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
2657 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
2658 "i %d last_cookie %d is same\n",
2659 i, pmon->mon_last_buf_cookie);
2660 drop_mpdu = true;
2661 pmon->rx_mon_stats.dup_mon_buf_cnt++;
2662 continue;
2663 }
2664
2665 desc_info =
2666 ath12k_dp_get_rx_desc(ar->ab->dp, msdu_list.sw_cookie[i]);
2667 msdu = desc_info->skb;
2668
2669 if (!msdu) {
2670 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
2671 "msdu_pop: invalid msdu (%d/%d)\n",
2672 i + 1, num_msdus);
2673 goto next_msdu;
2674 }
2675 rxcb = ATH12K_SKB_RXCB(msdu);
2676 if (rxcb->paddr != msdu_list.paddr[i]) {
2677 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
2678 "i %d paddr %lx != %lx\n",
2679 i, (unsigned long)rxcb->paddr,
2680 (unsigned long)msdu_list.paddr[i]);
2681 drop_mpdu = true;
2682 continue;
2683 }
2684 if (!rxcb->unmapped) {
2685 dma_unmap_single(ar->ab->dev, rxcb->paddr,
2686 msdu->len +
2687 skb_tailroom(msdu),
2688 DMA_FROM_DEVICE);
2689 rxcb->unmapped = 1;
2690 }
2691 if (drop_mpdu) {
2692 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
2693 "i %d drop msdu %p *ppdu_id %x\n",
2694 i, msdu, *ppdu_id);
2695 dev_kfree_skb_any(msdu);
2696 msdu = NULL;
2697 goto next_msdu;
2698 }
2699
2700 rx_desc = (struct hal_rx_desc *)msdu->data;
2701 l2_hdr_offset = ath12k_dp_rx_h_l3pad(ar->ab, tail_rx_desc);
2702 if (is_first_msdu) {
2703 if (!ath12k_wifi7_dp_rxdesc_mpdu_valid(ar->ab,
2704 rx_desc)) {
2705 drop_mpdu = true;
2706 dev_kfree_skb_any(msdu);
2707 msdu = NULL;
2708 pmon->mon_last_linkdesc_paddr = paddr;
2709 goto next_msdu;
2710 }
2711 msdu_ppdu_id =
2712 ath12k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
2713
2714 if (ath12k_dp_mon_comp_ppduid(msdu_ppdu_id,
2715 ppdu_id)) {
2716 spin_unlock_bh(&pmon->mon_lock);
2717 return rx_bufs_used;
2718 }
2719 pmon->mon_last_linkdesc_paddr = paddr;
2720 is_first_msdu = false;
2721 }
2722 ath12k_wifi7_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
2723 &is_frag, &total_len,
2724 &frag_len, &msdu_cnt);
2725 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
2726
2727 if (ath12k_dp_pkt_set_pktlen(msdu, rx_buf_size)) {
2728 dev_kfree_skb_any(msdu);
2729 goto next_msdu;
2730 }
2731
2732 if (!(*head_msdu))
2733 *head_msdu = msdu;
2734 else if (last)
2735 last->next = msdu;
2736
2737 last = msdu;
2738 next_msdu:
2739 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
2740 rx_bufs_used++;
2741 desc_info->skb = NULL;
2742 list_add_tail(&desc_info->list, used_list);
2743 }
2744
2745 ath12k_wifi7_hal_rx_buf_addr_info_set(&buf_info, paddr,
2746 sw_cookie, rbm);
2747
2748 ath12k_wifi7_dp_mon_next_link_desc_get(ab,
2749 msdu_link_desc, &paddr,
2750 &sw_cookie, &rbm,
2751 &p_buf_addr_info);
2752
2753 ath12k_dp_arch_rx_link_desc_return(ar->ab->dp, &buf_info,
2754 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
2755
2756 p_last_buf_addr_info = p_buf_addr_info;
2757
2758 } while (paddr && msdu_cnt);
2759
2760 spin_unlock_bh(&pmon->mon_lock);
2761
2762 if (last)
2763 last->next = NULL;
2764
2765 *tail_msdu = msdu;
2766
2767 if (msdu_cnt == 0)
2768 *npackets = 1;
2769
2770 return rx_bufs_used;
2771 }
2772
2773 /* The destination ring processing is stuck if the destination is not
2774 * moving while status ring moves 16 PPDU. The destination ring processing
2775 * skips this destination ring PPDU as a workaround.
2776 */
2777 #define MON_DEST_RING_STUCK_MAX_CNT 16
2778
2779 static void
ath12k_wifi7_dp_rx_mon_dest_process(struct ath12k * ar,int mac_id,u32 quota,struct napi_struct * napi)2780 ath12k_wifi7_dp_rx_mon_dest_process(struct ath12k *ar, int mac_id,
2781 u32 quota, struct napi_struct *napi)
2782 {
2783 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&ar->dp.mon_data;
2784 struct ath12k_pdev_mon_stats *rx_mon_stats;
2785 u32 ppdu_id, rx_bufs_used = 0, ring_id;
2786 u32 mpdu_rx_bufs_used, npackets = 0;
2787 struct ath12k_base *ab = ar->ab;
2788 struct ath12k_dp *dp = ath12k_ab_to_dp(ab);
2789 void *ring_entry, *mon_dst_srng;
2790 struct dp_mon_mpdu *tmp_mpdu;
2791 LIST_HEAD(rx_desc_used_list);
2792 struct hal_srng *srng;
2793
2794 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
2795 srng = &ab->hal.srng_list[ring_id];
2796
2797 mon_dst_srng = &ab->hal.srng_list[ring_id];
2798
2799 spin_lock_bh(&srng->lock);
2800
2801 ath12k_hal_srng_access_begin(ab, mon_dst_srng);
2802
2803 ppdu_id = pmon->mon_ppdu_info.ppdu_id;
2804 rx_mon_stats = &pmon->rx_mon_stats;
2805
2806 while ((ring_entry = ath12k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
2807 struct sk_buff *head_msdu, *tail_msdu;
2808
2809 head_msdu = NULL;
2810 tail_msdu = NULL;
2811
2812 mpdu_rx_bufs_used = ath12k_wifi7_dp_rx_mon_mpdu_pop(ar, mac_id,
2813 ring_entry,
2814 &head_msdu,
2815 &tail_msdu,
2816 &rx_desc_used_list,
2817 &npackets,
2818 &ppdu_id);
2819
2820 rx_bufs_used += mpdu_rx_bufs_used;
2821
2822 if (mpdu_rx_bufs_used) {
2823 dp->mon_dest_ring_stuck_cnt = 0;
2824 } else {
2825 dp->mon_dest_ring_stuck_cnt++;
2826 rx_mon_stats->dest_mon_not_reaped++;
2827 }
2828
2829 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) {
2830 rx_mon_stats->dest_mon_stuck++;
2831 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
2832 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n",
2833 pmon->mon_ppdu_info.ppdu_id, ppdu_id,
2834 dp->mon_dest_ring_stuck_cnt,
2835 rx_mon_stats->dest_mon_not_reaped,
2836 rx_mon_stats->dest_mon_stuck);
2837 spin_lock_bh(&pmon->mon_lock);
2838 pmon->mon_ppdu_info.ppdu_id = ppdu_id;
2839 spin_unlock_bh(&pmon->mon_lock);
2840 continue;
2841 }
2842
2843 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
2844 spin_lock_bh(&pmon->mon_lock);
2845 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
2846 spin_unlock_bh(&pmon->mon_lock);
2847 ath12k_dbg(ar->ab, ATH12K_DBG_DATA,
2848 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n",
2849 ppdu_id, pmon->mon_ppdu_info.ppdu_id,
2850 rx_mon_stats->dest_mon_not_reaped,
2851 rx_mon_stats->dest_mon_stuck);
2852 break;
2853 }
2854
2855 if (head_msdu && tail_msdu) {
2856 tmp_mpdu = kzalloc_obj(*tmp_mpdu, GFP_ATOMIC);
2857 if (!tmp_mpdu)
2858 break;
2859
2860 tmp_mpdu->head = head_msdu;
2861 tmp_mpdu->tail = tail_msdu;
2862 tmp_mpdu->err_bitmap = pmon->err_bitmap;
2863 tmp_mpdu->decap_format = pmon->decap_format;
2864 ath12k_wifi7_dp_mon_rx_deliver(&ar->dp, tmp_mpdu,
2865 &pmon->mon_ppdu_info, napi);
2866 rx_mon_stats->dest_mpdu_done++;
2867 kfree(tmp_mpdu);
2868 }
2869
2870 ring_entry = ath12k_hal_srng_dst_get_next_entry(ar->ab,
2871 mon_dst_srng);
2872 }
2873 ath12k_hal_srng_access_end(ar->ab, mon_dst_srng);
2874
2875 spin_unlock_bh(&srng->lock);
2876
2877 if (rx_bufs_used) {
2878 rx_mon_stats->dest_ppdu_done++;
2879 ath12k_dp_rx_bufs_replenish(ar->ab->dp,
2880 &dp->rx_refill_buf_ring,
2881 &rx_desc_used_list,
2882 rx_bufs_used);
2883 }
2884 }
2885
2886 static enum dp_mon_status_buf_state
ath12k_wifi7_dp_rx_mon_buf_done(struct ath12k_base * ab,struct hal_srng * srng,struct dp_rxdma_mon_ring * rx_ring)2887 ath12k_wifi7_dp_rx_mon_buf_done(struct ath12k_base *ab, struct hal_srng *srng,
2888 struct dp_rxdma_mon_ring *rx_ring)
2889 {
2890 struct ath12k_skb_rxcb *rxcb;
2891 struct hal_tlv_64_hdr *tlv;
2892 struct sk_buff *skb;
2893 void *status_desc;
2894 dma_addr_t paddr;
2895 u32 cookie;
2896 int buf_id;
2897 u8 rbm;
2898
2899 status_desc = ath12k_hal_srng_src_next_peek(ab, srng);
2900 if (!status_desc)
2901 return DP_MON_STATUS_NO_DMA;
2902
2903 ath12k_wifi7_hal_rx_buf_addr_info_get(status_desc, &paddr, &cookie, &rbm);
2904
2905 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
2906
2907 spin_lock_bh(&rx_ring->idr_lock);
2908 skb = idr_find(&rx_ring->bufs_idr, buf_id);
2909 spin_unlock_bh(&rx_ring->idr_lock);
2910
2911 if (!skb)
2912 return DP_MON_STATUS_NO_DMA;
2913
2914 rxcb = ATH12K_SKB_RXCB(skb);
2915 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
2916 skb->len + skb_tailroom(skb),
2917 DMA_FROM_DEVICE);
2918
2919 tlv = (struct hal_tlv_64_hdr *)skb->data;
2920 if (le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG) != HAL_RX_STATUS_BUFFER_DONE)
2921 return DP_MON_STATUS_NO_DMA;
2922
2923 return DP_MON_STATUS_REPLINISH;
2924 }
2925
2926 static enum hal_rx_mon_status
ath12k_wifi7_dp_mon_parse_rx_dest(struct ath12k_pdev_dp * dp_pdev,struct ath12k_mon_data * pmon,struct sk_buff * skb)2927 ath12k_wifi7_dp_mon_parse_rx_dest(struct ath12k_pdev_dp *dp_pdev,
2928 struct ath12k_mon_data *pmon,
2929 struct sk_buff *skb)
2930 {
2931 struct ath12k *ar = ath12k_pdev_dp_to_ar(dp_pdev);
2932 struct hal_tlv_64_hdr *tlv;
2933 struct ath12k_skb_rxcb *rxcb;
2934 enum hal_rx_mon_status hal_status;
2935 u16 tlv_tag, tlv_len;
2936 u8 *ptr = skb->data;
2937
2938 do {
2939 tlv = (struct hal_tlv_64_hdr *)ptr;
2940 tlv_tag = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG);
2941
2942 /* The actual length of PPDU_END is the combined length of many PHY
2943 * TLVs that follow. Skip the TLV header and
2944 * rx_rxpcu_classification_overview that follows the header to get to
2945 * next TLV.
2946 */
2947
2948 if (tlv_tag == HAL_RX_PPDU_END)
2949 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
2950 else
2951 tlv_len = le64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN);
2952
2953 hal_status = ath12k_wifi7_dp_mon_rx_parse_status_tlv(dp_pdev, pmon,
2954 tlv);
2955
2956 if (ar->monitor_started && ar->ab->hw_params->rxdma1_enable &&
2957 ath12k_wifi7_dp_mon_parse_rx_dest_tlv(dp_pdev, pmon, hal_status,
2958 tlv->value))
2959 return HAL_RX_MON_STATUS_PPDU_DONE;
2960
2961 ptr += sizeof(*tlv) + tlv_len;
2962 ptr = PTR_ALIGN(ptr, HAL_TLV_64_ALIGN);
2963
2964 if ((ptr - skb->data) > skb->len)
2965 break;
2966
2967 } while ((hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE) ||
2968 (hal_status == HAL_RX_MON_STATUS_BUF_ADDR) ||
2969 (hal_status == HAL_RX_MON_STATUS_MPDU_START) ||
2970 (hal_status == HAL_RX_MON_STATUS_MPDU_END) ||
2971 (hal_status == HAL_RX_MON_STATUS_MSDU_END));
2972
2973 rxcb = ATH12K_SKB_RXCB(skb);
2974 if (rxcb->is_end_of_ppdu)
2975 hal_status = HAL_RX_MON_STATUS_PPDU_DONE;
2976
2977 return hal_status;
2978 }
2979
2980 static enum hal_rx_mon_status
ath12k_wifi7_dp_mon_rx_parse_mon_status(struct ath12k_pdev_dp * dp_pdev,struct ath12k_mon_data * pmon,struct sk_buff * skb,struct napi_struct * napi)2981 ath12k_wifi7_dp_mon_rx_parse_mon_status(struct ath12k_pdev_dp *dp_pdev,
2982 struct ath12k_mon_data *pmon,
2983 struct sk_buff *skb,
2984 struct napi_struct *napi)
2985 {
2986 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
2987 struct dp_mon_mpdu *tmp;
2988 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
2989 enum hal_rx_mon_status hal_status;
2990
2991 hal_status = ath12k_wifi7_dp_mon_parse_rx_dest(dp_pdev, pmon, skb);
2992 if (hal_status != HAL_RX_MON_STATUS_PPDU_DONE)
2993 return hal_status;
2994
2995 list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) {
2996 list_del(&mon_mpdu->list);
2997
2998 if (mon_mpdu->head && mon_mpdu->tail)
2999 ath12k_wifi7_dp_mon_rx_deliver(dp_pdev, mon_mpdu,
3000 ppdu_info, napi);
3001
3002 kfree(mon_mpdu);
3003 }
3004
3005 return hal_status;
3006 }
3007
3008 static int
ath12k_wifi7_dp_rx_reap_mon_status_ring(struct ath12k_base * ab,int mac_id,int * budget,struct sk_buff_head * skb_list)3009 ath12k_wifi7_dp_rx_reap_mon_status_ring(struct ath12k_base *ab, int mac_id,
3010 int *budget, struct sk_buff_head *skb_list)
3011 {
3012 const struct ath12k_hw_hal_params *hal_params;
3013 int buf_id, srng_id, num_buffs_reaped = 0;
3014 enum dp_mon_status_buf_state reap_status;
3015 struct dp_rxdma_mon_ring *rx_ring;
3016 struct ath12k_mon_data *pmon;
3017 struct ath12k_skb_rxcb *rxcb;
3018 struct hal_tlv_64_hdr *tlv;
3019 void *rx_mon_status_desc;
3020 struct hal_srng *srng;
3021 struct ath12k_dp *dp;
3022 struct sk_buff *skb;
3023 struct ath12k *ar;
3024 dma_addr_t paddr;
3025 u32 cookie;
3026 u8 rbm;
3027
3028 ar = ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
3029 dp = ath12k_ab_to_dp(ab);
3030 pmon = &ar->dp.mon_data;
3031 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id);
3032 rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
3033
3034 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
3035
3036 spin_lock_bh(&srng->lock);
3037
3038 ath12k_hal_srng_access_begin(ab, srng);
3039
3040 while (*budget) {
3041 *budget -= 1;
3042 rx_mon_status_desc = ath12k_hal_srng_src_peek(ab, srng);
3043 if (!rx_mon_status_desc) {
3044 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3045 break;
3046 }
3047 ath12k_wifi7_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3048 &cookie, &rbm);
3049 if (paddr) {
3050 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
3051
3052 spin_lock_bh(&rx_ring->idr_lock);
3053 skb = idr_find(&rx_ring->bufs_idr, buf_id);
3054 spin_unlock_bh(&rx_ring->idr_lock);
3055
3056 if (!skb) {
3057 ath12k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3058 buf_id);
3059 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3060 goto move_next;
3061 }
3062
3063 rxcb = ATH12K_SKB_RXCB(skb);
3064
3065 dma_sync_single_for_cpu(ab->dev, rxcb->paddr,
3066 skb->len + skb_tailroom(skb),
3067 DMA_FROM_DEVICE);
3068
3069 tlv = (struct hal_tlv_64_hdr *)skb->data;
3070 if (le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG) !=
3071 HAL_RX_STATUS_BUFFER_DONE) {
3072 pmon->buf_state = DP_MON_STATUS_NO_DMA;
3073 ath12k_warn(ab,
3074 "mon status DONE not set %llx, buf_id %d\n",
3075 le64_get_bits(tlv->tl, HAL_TLV_HDR_TAG),
3076 buf_id);
3077 /* RxDMA status done bit might not be set even
3078 * though tp is moved by HW.
3079 */
3080
3081 /* If done status is missing:
3082 * 1. As per MAC team's suggestion,
3083 * when HP + 1 entry is peeked and if DMA
3084 * is not done and if HP + 2 entry's DMA done
3085 * is set. skip HP + 1 entry and
3086 * start processing in next interrupt.
3087 * 2. If HP + 2 entry's DMA done is not set,
3088 * poll onto HP + 1 entry DMA done to be set.
3089 * Check status for same buffer for next time
3090 * dp_rx_mon_status_srng_process
3091 */
3092 reap_status = ath12k_wifi7_dp_rx_mon_buf_done(ab, srng,
3093 rx_ring);
3094 if (reap_status == DP_MON_STATUS_NO_DMA)
3095 continue;
3096
3097 spin_lock_bh(&rx_ring->idr_lock);
3098 idr_remove(&rx_ring->bufs_idr, buf_id);
3099 spin_unlock_bh(&rx_ring->idr_lock);
3100
3101 dma_unmap_single(ab->dev, rxcb->paddr,
3102 skb->len + skb_tailroom(skb),
3103 DMA_FROM_DEVICE);
3104
3105 dev_kfree_skb_any(skb);
3106 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3107 goto move_next;
3108 }
3109
3110 spin_lock_bh(&rx_ring->idr_lock);
3111 idr_remove(&rx_ring->bufs_idr, buf_id);
3112 spin_unlock_bh(&rx_ring->idr_lock);
3113
3114 dma_unmap_single(ab->dev, rxcb->paddr,
3115 skb->len + skb_tailroom(skb),
3116 DMA_FROM_DEVICE);
3117
3118 if (ath12k_dp_pkt_set_pktlen(skb, RX_MON_STATUS_BUF_SIZE)) {
3119 dev_kfree_skb_any(skb);
3120 goto move_next;
3121 }
3122 __skb_queue_tail(skb_list, skb);
3123 } else {
3124 pmon->buf_state = DP_MON_STATUS_REPLINISH;
3125 }
3126 move_next:
3127 skb = ath12k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3128 &buf_id);
3129 hal_params = ab->hal.hal_params;
3130
3131 if (!skb) {
3132 ath12k_warn(ab, "failed to alloc buffer for status ring\n");
3133 ath12k_wifi7_hal_rx_buf_addr_info_set(rx_mon_status_desc,
3134 0, 0,
3135 hal_params->rx_buf_rbm);
3136 num_buffs_reaped++;
3137 break;
3138 }
3139 rxcb = ATH12K_SKB_RXCB(skb);
3140
3141 cookie = u32_encode_bits(mac_id, DP_RXDMA_BUF_COOKIE_PDEV_ID) |
3142 u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID);
3143
3144 ath12k_wifi7_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3145 cookie, hal_params->rx_buf_rbm);
3146 ath12k_hal_srng_src_get_next_entry(ab, srng);
3147 num_buffs_reaped++;
3148 }
3149 ath12k_hal_srng_access_end(ab, srng);
3150 spin_unlock_bh(&srng->lock);
3151
3152 return num_buffs_reaped;
3153 }
3154
3155 static int
__ath12k_wifi7_dp_mon_process_ring(struct ath12k * ar,int mac_id,struct napi_struct * napi,int * budget)3156 __ath12k_wifi7_dp_mon_process_ring(struct ath12k *ar, int mac_id,
3157 struct napi_struct *napi, int *budget)
3158 {
3159 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&ar->dp.mon_data;
3160 struct ath12k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats;
3161 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
3162 enum hal_rx_mon_status hal_status;
3163 struct sk_buff_head skb_list;
3164 int num_buffs_reaped;
3165 struct sk_buff *skb;
3166
3167 __skb_queue_head_init(&skb_list);
3168
3169 num_buffs_reaped = ath12k_wifi7_dp_rx_reap_mon_status_ring(ar->ab, mac_id,
3170 budget, &skb_list);
3171 if (!num_buffs_reaped)
3172 goto exit;
3173
3174 while ((skb = __skb_dequeue(&skb_list))) {
3175 memset(ppdu_info, 0, sizeof(*ppdu_info));
3176 ppdu_info->peer_id = HAL_INVALID_PEERID;
3177
3178 hal_status = ath12k_wifi7_dp_mon_parse_rx_dest(&ar->dp, pmon, skb);
3179
3180 if (ar->monitor_started &&
3181 pmon->mon_ppdu_status == DP_PPDU_STATUS_START &&
3182 hal_status == HAL_TLV_STATUS_PPDU_DONE) {
3183 rx_mon_stats->status_ppdu_done++;
3184 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
3185 ath12k_wifi7_dp_rx_mon_dest_process(ar, mac_id, *budget, napi);
3186 pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
3187 }
3188
3189 dev_kfree_skb_any(skb);
3190 }
3191
3192 exit:
3193 return num_buffs_reaped;
3194 }
3195
3196 static int
ath12k_wifi7_dp_mon_srng_process(struct ath12k_pdev_dp * pdev_dp,int * budget,struct napi_struct * napi)3197 ath12k_wifi7_dp_mon_srng_process(struct ath12k_pdev_dp *pdev_dp, int *budget,
3198 struct napi_struct *napi)
3199 {
3200 struct ath12k_dp *dp = pdev_dp->dp;
3201 struct ath12k_base *ab = dp->ab;
3202 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data;
3203 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info;
3204 struct hal_mon_dest_desc *mon_dst_desc;
3205 struct sk_buff *skb;
3206 struct ath12k_skb_rxcb *rxcb;
3207 struct dp_srng *mon_dst_ring;
3208 struct hal_srng *srng;
3209 struct dp_rxdma_mon_ring *buf_ring;
3210 struct ath12k_dp_link_peer *peer;
3211 struct sk_buff_head skb_list;
3212 u64 cookie;
3213 int num_buffs_reaped = 0, srng_id, buf_id;
3214 u32 hal_status, end_offset, info0, end_reason;
3215 u8 pdev_idx = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, pdev_dp->mac_id);
3216
3217 __skb_queue_head_init(&skb_list);
3218 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, pdev_idx);
3219 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id];
3220 buf_ring = &dp->rxdma_mon_buf_ring;
3221
3222 srng = &ab->hal.srng_list[mon_dst_ring->ring_id];
3223 spin_lock_bh(&srng->lock);
3224 ath12k_hal_srng_access_begin(ab, srng);
3225
3226 while (likely(*budget)) {
3227 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng);
3228 if (unlikely(!mon_dst_desc))
3229 break;
3230
3231 /* In case of empty descriptor, the cookie in the ring descriptor
3232 * is invalid. Therefore, this entry is skipped, and ring processing
3233 * continues.
3234 */
3235 info0 = le32_to_cpu(mon_dst_desc->info0);
3236 if (u32_get_bits(info0, HAL_MON_DEST_INFO0_EMPTY_DESC))
3237 goto move_next;
3238
3239 cookie = le32_to_cpu(mon_dst_desc->cookie);
3240 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID);
3241
3242 spin_lock_bh(&buf_ring->idr_lock);
3243 skb = idr_remove(&buf_ring->bufs_idr, buf_id);
3244 spin_unlock_bh(&buf_ring->idr_lock);
3245
3246 if (unlikely(!skb)) {
3247 ath12k_warn(ab, "monitor destination with invalid buf_id %d\n",
3248 buf_id);
3249 goto move_next;
3250 }
3251
3252 rxcb = ATH12K_SKB_RXCB(skb);
3253 dma_unmap_single(ab->dev, rxcb->paddr,
3254 skb->len + skb_tailroom(skb),
3255 DMA_FROM_DEVICE);
3256
3257 end_reason = u32_get_bits(info0, HAL_MON_DEST_INFO0_END_REASON);
3258
3259 /* HAL_MON_FLUSH_DETECTED implies that an rx flush received at the end of
3260 * rx PPDU and HAL_MON_PPDU_TRUNCATED implies that the PPDU got
3261 * truncated due to a system level error. In both the cases, buffer data
3262 * can be discarded
3263 */
3264 if ((end_reason == HAL_MON_FLUSH_DETECTED) ||
3265 (end_reason == HAL_MON_PPDU_TRUNCATED)) {
3266 ath12k_dbg(ab, ATH12K_DBG_DATA,
3267 "Monitor dest descriptor end reason %d", end_reason);
3268 dev_kfree_skb_any(skb);
3269 goto move_next;
3270 }
3271
3272 /* Calculate the budget when the ring descriptor with the
3273 * HAL_MON_END_OF_PPDU to ensure that one PPDU worth of data is always
3274 * reaped. This helps to efficiently utilize the NAPI budget.
3275 */
3276 if (end_reason == HAL_MON_END_OF_PPDU) {
3277 *budget -= 1;
3278 rxcb->is_end_of_ppdu = true;
3279 }
3280
3281 end_offset = u32_get_bits(info0, HAL_MON_DEST_INFO0_END_OFFSET);
3282 if (likely(end_offset <= DP_RX_BUFFER_SIZE)) {
3283 skb_put(skb, end_offset);
3284 } else {
3285 ath12k_warn(ab,
3286 "invalid offset on mon stats destination %u\n",
3287 end_offset);
3288 skb_put(skb, DP_RX_BUFFER_SIZE);
3289 }
3290
3291 __skb_queue_tail(&skb_list, skb);
3292
3293 move_next:
3294 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1);
3295 ath12k_hal_srng_dst_get_next_entry(ab, srng);
3296 num_buffs_reaped++;
3297 }
3298
3299 ath12k_hal_srng_access_end(ab, srng);
3300 spin_unlock_bh(&srng->lock);
3301
3302 if (!num_buffs_reaped)
3303 return 0;
3304
3305 /* In some cases, one PPDU worth of data can be spread across multiple NAPI
3306 * schedules, To avoid losing existing parsed ppdu_info information, skip
3307 * the memset of the ppdu_info structure and continue processing it.
3308 */
3309 if (!ppdu_info->ppdu_continuation)
3310 ath12k_wifi7_dp_mon_rx_memset_ppdu_info(ppdu_info);
3311
3312 while ((skb = __skb_dequeue(&skb_list))) {
3313 hal_status = ath12k_wifi7_dp_mon_rx_parse_mon_status(pdev_dp, pmon,
3314 skb, napi);
3315 if (hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
3316 ppdu_info->ppdu_continuation = true;
3317 dev_kfree_skb_any(skb);
3318 continue;
3319 }
3320
3321 if (ppdu_info->peer_id == HAL_INVALID_PEERID)
3322 goto free_skb;
3323
3324 rcu_read_lock();
3325 peer = ath12k_dp_link_peer_find_by_peerid(pdev_dp, ppdu_info->peer_id);
3326 if (!peer || !peer->sta) {
3327 ath12k_dbg(ab, ATH12K_DBG_DATA,
3328 "failed to find the peer with monitor peer_id %d\n",
3329 ppdu_info->peer_id);
3330 goto next_skb;
3331 }
3332
3333 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) {
3334 ath12k_dp_mon_rx_update_peer_su_stats(peer, ppdu_info);
3335 } else if ((ppdu_info->fc_valid) &&
3336 (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) {
3337 ath12k_dp_mon_rx_process_ulofdma(ppdu_info);
3338 ath12k_dp_mon_rx_update_peer_mu_stats(ab, ppdu_info);
3339 }
3340
3341 next_skb:
3342 rcu_read_unlock();
3343 free_skb:
3344 dev_kfree_skb_any(skb);
3345 ath12k_wifi7_dp_mon_rx_memset_ppdu_info(ppdu_info);
3346 }
3347
3348 return num_buffs_reaped;
3349 }
3350
ath12k_wifi7_dp_mon_process_ring(struct ath12k_dp * dp,int mac_id,struct napi_struct * napi,int budget,enum dp_monitor_mode monitor_mode)3351 int ath12k_wifi7_dp_mon_process_ring(struct ath12k_dp *dp, int mac_id,
3352 struct napi_struct *napi, int budget,
3353 enum dp_monitor_mode monitor_mode)
3354 {
3355 u8 pdev_idx = ath12k_hw_mac_id_to_pdev_id(dp->hw_params, mac_id);
3356 struct ath12k_pdev_dp *dp_pdev;
3357 struct ath12k *ar;
3358 int num_buffs_reaped = 0;
3359
3360 rcu_read_lock();
3361
3362 dp_pdev = ath12k_dp_to_pdev_dp(dp, pdev_idx);
3363 if (!dp_pdev) {
3364 rcu_read_unlock();
3365 return 0;
3366 }
3367
3368 if (dp->hw_params->rxdma1_enable) {
3369 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE)
3370 num_buffs_reaped = ath12k_wifi7_dp_mon_srng_process(dp_pdev,
3371 &budget,
3372 napi);
3373 } else {
3374 ar = ath12k_pdev_dp_to_ar(dp_pdev);
3375
3376 if (ar->monitor_started)
3377 num_buffs_reaped =
3378 __ath12k_wifi7_dp_mon_process_ring(ar, mac_id, napi,
3379 &budget);
3380 }
3381
3382 rcu_read_unlock();
3383
3384 return num_buffs_reaped;
3385 }
3386