xref: /linux/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml (revision 9e676a024fa1fa2bd8150c2d2ba85478280353bc) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm CMN PLL Clock Controller on IPQ SoC
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Luo Jie <quic_luoj@quicinc.com>
12
13description:
14  The CMN (or common) PLL clock controller expects a reference
15  input clock. This reference clock is from the on-board Wi-Fi.
16  The CMN PLL supplies a number of fixed rate output clocks to
17  the devices providing networking functions and to GCC. These
18  networking hardware include PPE (packet process engine), PCS
19  and the externally connected switch or PHY devices. The CMN
20  PLL block also outputs fixed rate clocks to GCC. The PLL's
21  primary function is to enable fixed rate output clocks for
22  networking hardware functions used with the IPQ SoC.
23
24properties:
25  compatible:
26    enum:
27      - qcom,ipq9574-cmn-pll
28
29  reg:
30    maxItems: 1
31
32  clocks:
33    items:
34      - description: The reference clock. The supported clock rates include
35          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
36      - description: The AHB clock
37      - description: The SYS clock
38    description:
39      The reference clock is the source clock of CMN PLL, which is from the
40      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
41      clock registers.
42
43  clock-names:
44    items:
45      - const: ref
46      - const: ahb
47      - const: sys
48
49  "#clock-cells":
50    const: 1
51
52required:
53  - compatible
54  - reg
55  - clocks
56  - clock-names
57  - "#clock-cells"
58
59additionalProperties: false
60
61examples:
62  - |
63    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
64    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
65
66    cmn_pll: clock-controller@9b000 {
67        compatible = "qcom,ipq9574-cmn-pll";
68        reg = <0x0009b000 0x800>;
69        clocks = <&cmn_pll_ref_clk>,
70                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
71                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
72        clock-names = "ref", "ahb", "sys";
73        #clock-cells = <1>;
74        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
75        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
76    };
77...
78