clk\-phase\- (full) in projects: linux - OpenGrok search results

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Searched +full:clk +full:- +full:phase +full:- (Results 1 – 14 of 14) sorted by relevance

/illumos-gate/usr/src/uts/sun/sys/
H A D	ser_zscc.h	34 * This is a dual uart chip with on-chip baud rate generators. 35 * It is about as brain-damaged as the typical modern uart chip, 37 * brain damage around addressing, write-onlyness, etc. 73 * bits in R/WR2 -- interrupt vector number. 95 * bits in RR3 -- Interrupt Pending flags for both channels (this reg can 105 /* bits in RR8 -- this is the same as reading the Data port / 107 / bits in RR10 -- DPLL and SDLC Loop Mode status -- not entered / 109 / bits in R/WR12 -- lower byte of time constant for baud rate generator / 110 / bits in R/WR13 -- upper byte of time constant for baud rate generator / 112 / bits in R/WR15 -- interrupt enables for status conditions */ [all …]
/illumos-gate/usr/src/uts/common/io/iwp/
H A D	iwp.c	103 #include "fw-iw/iwp.ucode" 495 if (sc->sc_flags & IWP_F_RUNNING) { in iwp_attach() 499 atomic_and_32(&sc->sc_flags, ~IWP_F_SUSPEND); in iwp_attach() 519 sc->sc_dip = dip; in iwp_attach() 524 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwp_attach() 525 &iwp_reg_accattr, &sc->sc_cfg_handle); in iwp_attach() 532 sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle, in iwp_attach() 533 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID)); in iwp_attach() 534 if ((sc->sc_dev_id != 0x422B) && in iwp_attach() 535 (sc->sc_dev_id != 0x422C) && in iwp_attach() [all …]
/illumos-gate/usr/src/uts/common/io/iwh/
H A D	iwh.c	107 #include "fw-iw/fw_5000/iwh_5000.ucode" 111 #include "fw-iw/fw_5150/iwh_5150.ucode" 530 if (sc->sc_flags & IWH_F_RUNNING) { in iwh_attach() 534 atomic_and_32(&sc->sc_flags, ~IWH_F_SUSPEND); in iwh_attach() 555 sc->sc_dip = dip; in iwh_attach() 560 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwh_attach() 561 &iwh_reg_accattr, &sc->sc_cfg_handle); in iwh_attach() 568 sc->sc_dev_id = ddi_get16(sc->sc_cfg_handle, in iwh_attach() 569 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_DEVID)); in iwh_attach() 570 if ((sc->sc_dev_id != 0x4232) && in iwh_attach() [all …]
/illumos-gate/usr/src/uts/common/io/iwk/
H A D	iwk2.c	91 #include "fw-iw/iw4965.ucode.hex" 493 mutex_enter(&sc->sc_glock); in iwk_attach() 494 sc->sc_flags &= ~IWK_F_SUSPEND; in iwk_attach() 495 mutex_exit(&sc->sc_glock); in iwk_attach() 497 if (sc->sc_flags & IWK_F_RUNNING) in iwk_attach() 500 mutex_enter(&sc->sc_glock); in iwk_attach() 501 sc->sc_flags \|= IWK_F_LAZY_RESUME; in iwk_attach() 502 mutex_exit(&sc->sc_glock); in iwk_attach() 519 sc->sc_dip = dip; in iwk_attach() 521 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0, in iwk_attach() [all …]
/illumos-gate/usr/src/uts/common/io/iwi/
H A D	ipw2200.c	71 * minimal size reserved in tx-ring 261 (((_c)->ich_flags & IEEE80211_CHAN_2GHZ) != 0) 263 (((_c)->ich_flags & IEEE80211_CHAN_5GHZ) != 0) 308 sc->sc_vendor = ddi_get16(cfgh, in ipw2200_setup_pci() 310 sc->sc_device = ddi_get16(cfgh, in ipw2200_setup_pci() 312 sc->sc_subven = ddi_get16(cfgh, in ipw2200_setup_pci() 314 sc->sc_subdev = ddi_get16(cfgh, in ipw2200_setup_pci() 316 IPW2200_DBG(IPW2200_DBG_WIFI, (sc->sc_dip, CE_CONT, in ipw2200_setup_pci() 319 sc->sc_vendor, sc->sc_device, sc->sc_subven, sc->sc_subdev)); in ipw2200_setup_pci() 352 IPW2200_DBG(IPW2200_DBG_SUSPEND, (sc->sc_dip, CE_CONT, in ipw2200_attach() [all …]
/illumos-gate/usr/src/uts/common/io/bge/
H A D	bge_impl.h	23 * Copyright (c) 2010-2013, by Broadcom, Inc. 93 ((uint32_t)((uint8_t )(&((_s )0)->_f) - \ 102 * as the typedef for ether_addr_t ;-! 120 * Compile-time feature switches ... 132 * register-set numbers to use for the config space registers 133 * and the operating registers respectively. On an OBP-based 145 * has been stripped off, the packet data will be 4-byte aligned. 182 * are derived from observations and heuristics - the values below 223 * 570X-PG102-R page 56. 259 * PCI type. PCI-Express or PCI/PCIX [all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A D	hxge_peu_hw.h	230 * Master Data Parity Error - set if all the following conditions 234 * Fast Back-to-Back Capable (N/A in PCIE) 236 * Capabilities List - presence of extended capability item. 239 * Fast Back-to-Back Enable (N/A in PCIE) 244 * The device can issue Memory Write-and-Invalidate commands (N/A 346 * Multi-Function Device: dbi writeable 374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0 432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX 489 * Description: Virtualization BAR0 - Previously for Hydra 566 * Subsystem ID as assigned by PCI-SIG : dbi writeable [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	57712_reg.h	3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32 9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 16 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 17 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/
H A D	bnxe_clc.c	55 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 83 #define OFFSETOF(_s, _m) ((u32) ((u8 )(&((_s ) 0)->_m) - \ 148 #define CHIP_REV_SIM(_p) (((0xF - (CHIP_REV(_p) >> CHIP_REV_SHIFT)) \ 329 (_phy)->def_md_devad, \ 335 (_phy)->def_md_devad, \ 365 * elink_check_lfa - This function checks if link reinitialization is required, 378 struct elink_dev cb = params->cb; in elink_check_lfa() 381 REG_RD(cb, params->lfa_base + in elink_check_lfa() 384 / NOTE: must be first condition checked - in elink_check_lfa() 389 REG_WR(cb, params->lfa_base + in elink_check_lfa() [all …]