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/linux/drivers/clk/meson/
H A Dclk-phase.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <linux/clk-provider.h>
10 #include "clk-regmap.h"
11 #include "clk-phase.h"
16 meson_clk_phase_data(struct clk_regmap *clk) in meson_clk_phase_data() argument
18 return (struct meson_clk_phase_data *)clk->data; in meson_clk_phase_data()
39 struct clk_regmap *clk = to_clk_regmap(hw); in meson_clk_phase_get_phase() local
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
[all …]
/linux/include/trace/events/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #define TRACE_SYSTEM clk
15 DECLARE_EVENT_CLASS(clk,
22 __string( name, core->name )
32 DEFINE_EVENT(clk, clk_enable,
39 DEFINE_EVENT(clk, clk_enable_complet
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/linux/drivers/clk/rockchip/
H A Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
12 #include "clk.h"
40 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
53 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase()
57 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
85 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase()
96 pr_err("%s: invalid clk rate\n", __func__); in rockchip_mmc_set_phase()
97 return -EINVAL; in rockchip_mmc_set_phase()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
8 clk-rockchip-y += clk.o
9 clk-rockchip-y += clk-pll.o
10 clk-rockchip-y += clk-cpu.o
11 clk-rockchip-y += clk-half-divider.o
12 clk-rockchip-y += clk-inverter.o
13 clk-rockchip-y += clk-mmc-phase.o
14 clk-rockchip-y += clk-muxgrf.o
15 clk-rockchip-y += clk-ddr.o
[all …]
/linux/drivers/mmc/core/
H A Dhost.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2007-2008 Pierre Ossman
24 #include <linux/mmc/slot-gpio.h>
29 #include "slot-gpio.h"
46 if (!host->bus_ops) in mmc_host_class_prepare()
50 if (host->bus_ops->pre_suspend) in mmc_host_class_prepare()
51 return host->bus_ops->pre_suspend(host); in mmc_host_class_prepare()
76 wakeup_source_unregister(host->ws); in mmc_host_classdev_release()
77 if (of_alias_get_id(host->parent->of_node, "mmc") < 0) in mmc_host_classdev_release()
78 ida_free(&mmc_host_ida, host->index); in mmc_host_classdev_release()
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/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
8 #include <linux/dma-mapping.h>
71 int phase, bool sampler __maybe_unused);
84 struct sdmmc_idma *idma = host->dma_priv; in sdmmc_idma_validate_data()
85 struct device *dev = mmc_dev(host->mmc); in sdmmc_idma_validate_data()
93 idma->use_bounce_buffer = false; in sdmmc_idma_validate_data()
94 for_each_sg(data->sg, sg, data->sg_len - 1, i) { in sdmmc_idma_validate_data()
95 if (!IS_ALIGNED(sg->offset, sizeof(u32)) || in sdmmc_idma_validate_data()
96 !IS_ALIGNED(sg->length, in sdmmc_idma_validate_data()
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H A Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
33 struct clk *drv_clk;
34 struct clk *sample_clk;
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()
51 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_internal_phase()
78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
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H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
101 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
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H A Ddw_mmc-hi3798mv200.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Modified from dw_mmc-hi3798cv200.c
9 #include <linux/clk.h>
18 #include "dw_mmc-pltfm.h"
29 struct clk *sample_clk;
30 struct clk *drive_clk;
38 struct dw_mci_hi3798mv200_priv *priv = host->priv; in dw_mci_hi3798mv200_set_ios()
39 struct mmc_clk_phase phase = priv->phase_map.phase[ios->timing]; in dw_mci_hi3798mv200_set_ios() local
43 if (ios->timing == MMC_TIMING_MMC_DDR52 in dw_mci_hi3798mv200_set_ios()
44 || ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798mv200_set_ios()
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H A Dsdhci-of-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include <linux/clk.h>
18 #include "sdhci-pltfm.h"
40 struct clk *clk; member
85 * -----|-------------|----------|------------
108 writel(cap_val, sdc->regs + mirror_reg_offset); in aspeed_sdc_set_slot_capability()
118 spin_lock(&sdc->lock); in aspeed_sdc_configure_8bit_mode()
119 info = readl(sdc->regs + ASPEED_SDC_INFO); in aspeed_sdc_configure_8bit_mode()
121 info |= sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
123 info &= ~sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
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H A Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
137 /* Max load for eMMC Vdd-io supply */
141 msm_host->var_ops->msm_readl_relaxed(host, offset)
144 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
263 struct clk *bus_clk; /* SDHC bus voter clock */
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/linux/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c1 // SPDX-License-Identifier: GPL-2.0
5 * Simple HiSilicon phase clock implementation.
14 #include "clk.h"
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
39 return -EINVAL; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o
8 obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
9 obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
10 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
12 obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
13 obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o
14 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
15 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
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/linux/Documentation/devicetree/bindings/clock/
H A Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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/linux/drivers/watchdog/
H A Drealtek_otto_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
11 * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
12 * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
13 * Generates an interrupt, WDT cannot be stopped after phase 1
14 * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
20 #include <linux/clk.h>
54 * One higher than the max values contained in PHASE{1,2}, since a value of 0
79 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
81 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
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/linux/drivers/clk/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
25 #include "clk.h"
86 int phase; member
100 #include <trace/events/clk.h>
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/linux/drivers/counter/
H A Drz-mtu3-cnt.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk.h>
10 #include <linux/mfd/rz-mtu3.h>
31 #define RZ_MTU3_TMDR1_PH_CNT_MODE_1 (4) /* Phase counting mode 1 */
32 #define RZ_MTU3_TMDR1_PH_CNT_MODE_2 (5) /* Phase counting mode 2 */
33 #define RZ_MTU3_TMDR1_PH_CNT_MODE_3 (6) /* Phase counting mode 3 */
34 #define RZ_MTU3_TMDR1_PH_CNT_MODE_4 (7) /* Phase counting mode 4 */
35 #define RZ_MTU3_TMDR1_PH_CNT_MODE_5 (9) /* Phase counting mode 5 */
40 * 0: 16-bit, 1: 32-bit
45 * PHCKSEL: External Input Phase Clock Select
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
53 int modulo, phase; in dccg2_update_dpp_dto() local
55 // phase / modulo = dpp pipe clk / dpp global clk in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
59 if (phase > 0xff) { in dccg2_update_dpp_dto()
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu_phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
32 return -EINVAL; in ccu_phase_get_phase()
37 return -EINVAL; in ccu_phase_get_phase()
42 return -EINVAL; in ccu_phase_get_phase()
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/linux/drivers/iio/dac/
H A Dadi-axi-dac.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2016-2024 Analog Devices Inc.
11 #include <linux/clk.h>
26 #include <linux/fpga/adi-axi-common.h>
28 #include <linux/iio/buffer-dmaengine.h>
91 guard(mutex)(&st->lock); in axi_dac_enable()
92 ret = regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN, in axi_dac_enable()
101 ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS, __val, in axi_dac_enable()
106 return regmap_set_bits(st->regmap, AXI_DAC_REG_RSTN, in axi_dac_enable()
114 guard(mutex)(&st->lock); in axi_dac_disable()
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/linux/drivers/clk/tegra/
H A Dclk-device.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/clk.h>
4 #include <linux/clk-provider.h>
15 #include "clk.h"
33 struct device *dev = clk_dev->dev; in tegra_clock_set_pd_state()
38 if (opp == ERR_PTR(-ERANGE)) { in tegra_clock_set_pd_state()
44 * not error out clk initialization. A typical example is in tegra_clock_set_pd_state()
71 mutex_lock(&clk_dev->lock); in tegra_clock_change_notify()
74 if (cnd->new_rate > cnd->old_rate) in tegra_clock_change_notify()
75 err = tegra_clock_set_pd_state(clk_dev, cnd->new_rate); in tegra_clock_change_notify()
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/linux/Documentation/devicetree/bindings/watchdog/
H A Dstarfive,jh7100-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
15 has only one timeout phase and reboots. And JH7110 watchdog has two
16 timeout phases. At the first phase, the signal of watchdog interrupt
25 - enum:
26 - starfive,jh7100-wdt
[all …]
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
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/linux/drivers/scsi/
H A Dinitio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 1994-1998 Initio Corporation
14 * This is the Linux low-level SCSI driver for Initio INI-9X00U/UW SCSI host
17 * 08/06/97 hc - v1.01h
18 * - Support inic-940 and inic-935
19 * 09/26/97 hc - v1.01i
20 * - Make correction from J.W. Schultz suggestion
21 * 10/13/97 hc - Support reset function
22 * 10/21/97 hc - v1.01j
23 * - Support 32 LUN (SCSI 3)
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